An energy-aware active smart card

Tessier, Russell; Jasinski, David; Maheshwari, A.; Natarajan, Aiyappan; Xu, Weifeng; Burleson, Wayne

doi:10.1109/tvlsi.2005.859471

Cited by 25 publications

(6 citation statements)

References 10 publications

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“…For devices such as smart cards, working around 13.56 MHz frequency, the adiabatic logic technique seems to be one of the attractive solutions to achieve low-power operation [9]. The energy dissipation of the adiabatic circuits infinitesimally tends to zero if the switching time is slowed down.…”

Section: Adiabatic Logic Techniquementioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ringcounter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.

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Section: Adiabatic Logic Techniquementioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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“…The study in this paper was limited to evaluation of phased inverters, and did not address dynamic logic or Smart Card cells. In [235]…”

Section: Low Power Medical Device Encryptionmentioning

confidence: 99%

Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security Applications

Morrison

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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To my parents, Alfred and Kathleen Morrison, and to my grandparents, Arthur and Betty Kempf, and Alfred and Dorothy Morrison, for making all the opportunities I have possible. ACKNOWLEDGMENTS I would like to thank my advisor, Dr. Nagarajan Ranganathan, for giving me the opportunity to pursue my research, and for his valuable guidance and assistance over these last four years. Ranga has always been an excellent motivator, guider, and leader, and completion of this project would not have been possible without his patience and belief in my ideas. I want to

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“…In VLSI, the transfer of the electric charge between nodes of circuit is considered. There are various techniques used to minimal power loss during a transient state [1]- [3]. The full adiabatic function circuit is one of the best conditions.…”

Section: Introductionmentioning

confidence: 99%

Power Efficient Technique for CMOS- Logic Circuits

Adhikari

Sahil

Naidu

et al. 2022

J. Phys.: Conf. Ser.

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Power outages on normal CMOS circuit is very high it can be reduced by using the adiabatic technique. Adiabatic technique is used in the pull up part of CMOS logic. Power loss of CMOS Logic is in terms of heat. Adiabatic is an efficient technique where some of the energy stored in the load and it is used for next inputs without dissipating as heat. The adiabatic technique depends largely on the parameter variation. With the help of DSCH, MICROWIND, TANNER EDA (S-edit, TWV, TSP) Software’s power consumed by ECRL (Efficient Charge Recovery Logic) is compared to the power consumed by common CMOS for NAND and NOR inverter circuits. In this study it is find out that the adiabatic technique is the good choice rather than conventional technique in terms of power consumption.

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An energy-aware active smart card

Cited by 25 publications

References 10 publications

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security Applications

Power Efficient Technique for CMOS- Logic Circuits

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