An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications

Duran, Ckristian; Wachs, Megan; Rueda, Ernesto; Huntington, Albert; Ardila, Javier; Kang, Jack; Amaya, Andres; Gomez, Hector; Romero, Juan; Fernandez, Laude; Flechas, Felipe; Torres, Rolando; Moya, Juan Sebastian; Ramirez, Wilmer; Arenas, Julian; Gómez, José Manuel; Morales, Hanssel; Rojas, Camilo; Mantilla, Alex; Roa, Elkim; Asanović, Krste

doi:10.1109/cicc48029.2020.9075877

Cited by 9 publications

(3 citation statements)

References 5 publications

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“…Fig. 7 shows the micro‐photograph of the fabricated multi‐throughput TRNG, embedded in a RISC‐V‐based SoC for periodical‐driven applications [9]. The TRNG was fabricated in the conventional TSMC 180 nm process, is fully synthesisable, and occupies an area of

150 μ m \times 58 μ m

.…”

Section: Measurement Resultsmentioning

confidence: 99%

Low‐cost TRNG IPs

Gomez

Arenas

Roa

2020

IET Circuits, Devices & Systems

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150 μ m \times 58 μ m

.…”

Section: Measurement Resultsmentioning

confidence: 99%

Low‐cost TRNG IPs

Gomez

Arenas

Roa

2020

IET Circuits, Devices & Systems

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“…The open-source RISC-V ISA and toolchain ecology provide the corresponding research foundation. For 32-bit fixedpoint MCU products, RISC-V ISA is classified based on modular standards, including I (Basic Instructions), M (Multiply/Divide Instructions), A (Atomic Instructions), and C (Compressed Instructions) [7,8,9,10,11,12,13,14]. At this stage, there are two types of related research in the RISC-V ISA and architecture design.…”

Section: Introductionmentioning

confidence: 99%

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

Meng

2022

IEICE Electron. Express

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With the increasing energy-efficiency requirements for the edge computing platforms, the Instruction Set Architecture (ISA) design and precision tuning techniques highlight the possibility of improving the efficiency of dedicated operations. RISC-V as an open-source instruction set shows excellent application potential. On the other hand, the modular ISA design brings elegant design ideas, and designers can pay more attention to the collaborative design of essential ISA and software libraries. To support the design of efficient precision tuned applications, this paper presents some novel architecture and software co-design based on integer and fixed-point computations. Based on a collection of RISC-V instruction custom designs for a fixed-point mathematics library, we propose an optimal decisionmaking methodology for the customized ISA design space exploration to optimize some dedicated algorithms.

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“…1 shows the energy consumption, normalized to an ADD operation in the ALU, of accessing SRAM or DRAM memories [1]. Since battery-constraint systems can operate in minimum energy supply operation (MESO) [2], reported cryptography accelerators optimize the power-speed trade-off and device's energy [3], [4].…”

Section: Introductionmentioning

confidence: 99%

AES Sbox Acceleration Schemes for Low-Cost SoCs

Duran

Gomez

Roa

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Current solutions for low-cost and secure systems have ended up trading effective encryption schemes for lighter encryption schemes to ensure longevity in battery-powered applications. Here we demonstrate the potential to apply an effective and lighter encryption scheme, such as AES-256, in a low-cost battery-powered systems-on-chip (SoC) without demanding excessive energy. We accelerated AES-256 with a custom instruction along with an enhanced memory access scheme. Measurement results from a fabricated SoC featuring a RISC-V based 32-bit processor indicate a 900 fold improvement of AES-256 computing energy efficiency compared to pure-software implementations. The memory access improves the energy by 3 times an standard push-pull hardware implementation.

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An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications

Cited by 9 publications

References 5 publications

Low‐cost TRNG IPs

Low‐cost TRNG IPs

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

AES Sbox Acceleration Schemes for Low-Cost SoCs

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