An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

Abstract

Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64 × 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4 × 4 to 64 × 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@3840 × 2.160 for 4 × 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64 × 64 size. INDEX TERMS FPGA, hardware architecture, multiple transform selection, pipeline, SoPC, versatile video coding. * The architecture proposed in this paper has been implemented and tested in accordance with WD 4. † The number of multiplications required by a direct implementation of a 2D N×N point DCT/DST is N 2 .

Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

“…64×64). The only work found in the literature that supports all MTS types and sizes in 2-D was proposed in [31]. This work is an extension of the architectures proposed by Garrido et al in [27] and [28].…”

“…Table XI and XII give the key performance of state-of-the-art FPGA and ASICbased works, respectively. The only work that supports all MTS types and sizes is found in [31] and its performance is presented in Table XI for FPGA platform. Compared to our MTS design on FPGA platform, we consume more resources in terms of Adaptive Logic Modules (ALMs) and registers, but on the other hand, we do not use any additional memory.…”

HLS and FPGA-Powered Streaming Video Encoder Accelerator for IoTs Edge Computing

“…Pastuszak [11] designed and developed an ASIC accelerator core utilizing the 90-nm TSMC technology to enhance the performance of the HEVC video encoder, achieving notable performance improvements through the ASIC (Application Specific Integrated Circuits) approach. Additionally, Garrido and Pescador et al [12] proposed a method for Versatile Video Coding (VVC) that emphasizes the transformation step, specifically the 64×64 2D discrete sine/cosine transforms, rather than addressing the entire encoding process.…”

Hardware architecture optimization for high-frequency zeroing and LFNST in H.266/VVC based on FPGA

“…Bianca et al [8,9] introduced a dedicated hardware architecture for the VVC MTS (Matrix-based Transform Skip) module, supporting all 16D transform combinations allowed by the MTS tool for both intra and inter prediction blocks but lacking support for full-size MTS transform sizes. Garrido et al [10,11,12] proposed a pipelined structure for twodimensional transforms based on general multipliers. They arranged dual-port Static Random-Access Memory (SRAM) in a matrix form for transpose storage, utilized First Input First Output (FIFO) queues to cache block information but faced the drawback of large area occupation by the transpose memory.Fan et al [13] proposed DST-VII and DCT-VIII transform structures supporting mixed-block processing.…”