An Fpga-Based Platform for a Network Architecture With Delay Guarantee

Abstract

The background that underlies this work is the envisioned real-time tele-immersive collaboration system for the future that supports delay-sensitive applications involving participants from remote places via their collaboration spaces (CSs). The end-to-end delay as high as 20 ms is required for good synchronization of such applications, for example collaborative dancing and remote conducting of choir. It is much lower than that facilitated by existing teleconference systems. A novel network architecture with delay guarantee, namely Distributed Multimedia Plays (DMP), has been proposed and designed to realize the vision. The maximum low latency is guaranteed because DMP network nodes can drop DMP packets of multimedia data from the CSs due to instantaneous traffic condition. Besides ultrafast processing time, modularity, and scalability must be taken into account in hardware design and implementation of the nodes for seamless incorporation of the modules. These lead us to employing field-programmable gate array (FPGA) due to its substantial computational power and flexibility. This paper presents an FPGA-based platform for the design and implementation of DMP network nodes. It provides a detailed introduction to the platform architecture and the simulation-implementation environment for the design. The modularity of the implemented node is shown by addressing three important modules for packet dropping, 3D warping, and image transform. Our compact implementation of the network node on Xilinx Virtex-6 ML605 mostly consumes very small amount of available resources. Moreover the elementary operations on our implementation takes (much) less than 5 μs as desired to meet the low-latency requirement.

Evaluation and Implementation of n-Gram-Based Algorithm for Fast Text Comparison

“…The authors are going to implement the parts of the algorithm as hardware modules in the future [21,22]. The most suitable for hardware implementation are the modules that perform massive parallel pattern matching such as fingerprint comparison [23,24,25,26,27].…”

Fpga Implementation of Procedures for Video Quality Assessment

“…The main concern of the authors of the papers is an efficient hardware implementation of proposed solution. This is addressed using hardware development techniques decreasing latency and throughput of the system which is a challenging task partially covered in the following papers [13][14][15][16][17].…”

Ultrafast Scalable Embedded DCT Image Coding for Tele-immersive Delay-Sensitive Collaboration

“…We have proposed an FPGA-based platform for the design and implementation of a DMP network node [31] (Fig. 15).…”