An FPGA-based VLIW processor with custom hardware execution

Abstract

The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

Multi-ported memories for FPGAs via XOR

“…Simple replication provides the 1W/2R register file required to support a three-operand ISA [1,5,6,10,15]. Jones et al [7] implement a VLIW soft processor with a multi-ported register file implemented entirely in logic elements, limiting the operating frequency. Saghir et al [12,13] also implement a multi-ported register file for a VLIW soft-processor, but use replication and banking of BRAMs; however, their compiler must schedule register accesses to avoid conflicting reads and writes.…”

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

“…Each functional unit consists of a 256x8-bit memory, an 8-bit ALU and a control logic. The Garp [23], the Chimaera [28], the MorphoSys [24], and the SuperCISC [20] architectures combine a reconfigurable computing device with a processor in order to do hardware acceleration. RaPiD (Reconfigurable Pipelined Datapath) [7,15], mainly intended for computation-intensive applications, consists of a linear array of application-specific functional units.…”

Customizing the Datapath and ISA of Soft VLIW Processors

“…In [13,14], the authors describe a soft VLIW processor consisting of four, identical, 32-bit ALUs and a customizable hardware block for accelerating performancecritical loop kernels. The ALUs and the hardware block operate in parallel and are interconnected through a single, multi-ported, 32 × 32-bit register file.…”