An Implementation of Wide-Range Digital Delay Locked Loop

Abstract

This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. The experimental result shows that the chip could work in a wide frequency range from 10 MHz to 1 GHz, with less than 20 cycles lock-in time, 10-ps delay resolution, and 6.4 mW at 1 GHz power dissipation.