An improved wide-range, low-complexity, fully-parallel digital background timing mismatch calibration method for dual-channel TIADC based on perfect reconstruction filter bank

Liu, Yu; Zhang, Zhenwei; Xiong, Wei; Sun, Lin; Lang, Lili; Wu, Xufan; Dong, Yemin

doi:10.1016/j.aeue.2023.154910

Cited by 4 publications

(1 citation statement)

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“…Most compensation methods rely on either filtering techniques [18][19][20][21] or Taylor expansion [11,22,23]. Numerous structures of the commonly employed filter are subjects of the study, with a substantial portion of researchers directing their investigations toward fractional-delay filters and perfect-reconstruction filters.…”

Section: Introductionmentioning

confidence: 99%

An All-Digital Timing Mismatch Calibration Algorithm Based on Reference Channel for TIADC

Zhong,

Dong,

Lang

et al. 2024

Electronics

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This paper proposes an all-digital calibration algorithm that utilizes a reference channel to suppress the timing mismatch in the Time-Interleaved Analog-to-Digital Converter (TIADC). The output of the reference channel is aligned with each sub-channel in turn, therefore enabling the simultaneous sampling and conversion of the same input signal. First, the statistical characteristics across the channels are employed for estimating the timing mismatch; then, by comparing the output difference between the reference channel and the sub-channels that are sampled simultaneously, the deviation of the derivator can be calibrated. Finally, combining both calibration results yields an accurate final output. This proposed algorithm provides an effective solution to improve TIADC performance in high-speed data acquisition systems. The proposed architecture is applied to a 12-bit 2.4 GS/s four-channel TIADC model, and then its effectiveness is verified. The simulation results exhibit that the Effective Number Of Bits (ENOB) at an input signal frequency of 984 MHz shows a remarkable improvement from 6.88 bits to 11.92 bits. The effectiveness of this technique is also demonstrated through the off-chip calibration of a commercial 12-bit four-channel 2 GS/s TIADC using a 680 MHz input signal that is based on the actual chip results.

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