An Inductive-Coupling Inter-Chip Link for High-Performance and Low-Power 3D System Integration

Niitsu, Kiichi; Kuroda, Tadahiro

doi:10.5772/6885

Cited by 4 publications

(1 citation statement)

References 20 publications

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“…In addition, 3D integration can solve the interconnection-related challenges, such as delays and power dissipation [3]. 3D integration is classified by the methods of interconnection, such as wire bonding [4], edge connecting, capacitive or inductive coupling [5], and direct contact using through silicon via (TSV) [6]. To date, wire bonding is widely used in device packaging because the existing facilities can be used and it has a high degree of freedom in connecting chips to substrates.…”

Section: Introductionmentioning

confidence: 99%

Analysis of a metal filling and liner formation mechanism of the blind via with nano-Ag particles for TSV (through silicon via) interconnection

Ham

Kim

Baek

et al. 2012

J. Micromech. Microeng.

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We investigated a metal filling and liner formation mechanism with a nano-Ag particle for the blind Si via, which is used in the via first process of through silicon via (TSV) interconnection. Using the deep reactive ion etching process, we produced the blind Si via (which is called the blind via hole or via) with a nearly vertical profile. The diameter and depth of the blind Si via were about 10 and 71 µm, respectively. The blind via holes were filled with a nano-Ag particle solution to form a metal plug or a metal liner. At this time, the Ag filling properties were monitored as a function of the volatilization rate of the Ag particle solution in the evacuating chamber. In the fast volatilization of the nano-Ag particle solution, an Ag liner formed on the inner wall of via holes. Meanwhile, both an Ag liner at the sidewall and the Ag plug at the bottom were obtained by the slow volatilization process. Finally, blind via holes fully filled with nano-Ag particles were obtained using four repetitions of the slow volatilization filling process. The proposed TSV filling process can fill large-diameter via holes over 100 µm without a seed layer and chemical mechanical planarization for TSV interconnection at low temperature. This is a simple and cost-effective TSV filling process.

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