An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs

Bhojwani, Praveen S.; Mahapatra, Rabi

doi:10.1109/isqed.2007.35

Cited by 7 publications

(13 citation statements)

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“…Taking this concept a step further, [4,5] constructed a Test Infrastructure IP (TI-IP) capable of managing test scheduling, delivery, and intrusion for concurrent on-line test (COLT) of the SoC. COLT allows cores in the SoC to be tested in the presence of normally executing applications to maximize system availability.…”

Section: A Concurrent On-line Testing (Colt)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Because the most significant electronic wear-out mechanisms manifest as an increasingly severe delay fault at the circuit level, many researchers have proposed the use of SCAN-based delay testing for detecting this type of error [4,14,15]. Built-in self-test (BIST) architectures using pseudo-randomly generated test vectors are effective in discovering wear-out in memory elements.…”

Section: Introductionmentioning

confidence: 99%

“…In the COLT strategies currently proposed in research, the delivery of test vectors from the test source (on-chip test storage or off-chip memory) to the individual cores Jason D. Lee [4,15]. This problem will only become more critical as the number of cores per SoC increases over time.…”

Section: Introductionmentioning

confidence: 99%

“…These tests can be applied as an isolated process -the entire system is taken off-line periodically or triggered by an event so that all cores can be tested for wear-out [16]. Alternatively, core testing can be performed concurrently with normally executing applications [4,5,15,16].Concurrent on-line test (COLT) exploits the massive structural redundancy of multi-and many-core architectures by shutting down some subset of cores within the SoC for testing while the remaining cores run user applications as normal. This allows the system to achieve its reliability requirements and maintain an extremely high level of availability.…”

mentioning

confidence: 99%

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A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems

Lee¹,

Mahapatra²,

Bhojwani

2009

2009 IEEE International Conference on Computer Design

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Abstract-Concurrent on-line testing (COLT) of manycore systems-on-chip (SoC) has been recently proposed by researchers in response to the growing threat of electronic wear-out to system operational lifetimes and to the increasing reliability and availability demands of safety-critical applications. Previous research in concurrent on-line testing has focused on centralized approaches to manage core testing while the system is available to execute normal user applications. However, as technology scaling allows dozens and hundreds of processing cores to be placed on a single chip, these centralized approaches are not scalable solutions. In this paper, a distributed concurrent on-line test scheduling protocol is proposed and evaluated against previously developed solutions. Our experiments show that a distributed COLT scheduler can test a moderately-sized SoC with a speedup of 3.85 over centralized approaches while consuming 84% less energy, and performance benefits improve as the number of cores per chip increases. This research also presents a core test ordering algorithm -Code-Division Core Test Scheduling -that provides an additional 40% reduction in system test latency compared to other schedulers. I. INTRODUCTIONRapid technology scaling has forced systems designers, reliability engineers and application programmers to rethink the fundamental design practices that have dominated computer system design for more than the past two decades. Multi-core systems-on-chip (SoC), with a handful of complex processing cores and integrated peripheral components, are predicted to be replaced by many-core SoC that contain hundreds or thousands of lightweight processing cores, memory and I/O subsystems. These many-core SoC will use packet switched networkson-chip (NoC) for inter-core communication, as opposed to the current standard of on-chip busses, [1,7]. Notable examples of this architecture include the 64-core TILE64 from TILERA [24] and the 80-core Intel Terascale SoC [11].As technology scaling has provided new opportunities for massively parallel and distributed computation to be performed on a single chip, new reliability challenges have also emerged. In addition to the well-understood circuit failures due to manufacturing imperfections, SoC components are also more susceptible to electronic wearout -permanent failures that emerge during use -as feature sizes scale below 65nm [2,6,7].In actuality, electronic wear-out is a combination of several physical degradation mechanisms, including electro-migration (EM), hot carrier injection (HCI) and negative bias temperature instability (NBTI), that are intensified by smaller feature sizes, higher current and power densities, and higher operating temperatures [2].Because the most significant electronic wear-out mechanisms manifest as an increasingly severe delay fault at the circuit level, many researchers have proposed the use of SCAN-based delay testing for detecting this type of error [4,14,15]. Built-in self-test (BIST) architectures using pseudo-randomly generated test v...

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Section: A Concurrent On-line Testing (Colt)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%