An integrated environment for HDL verification

York, Gary; Mueller-Thuns, R.B.; Patel, Janakkumar B.; Beatty, Derek L.

doi:10.1109/ivc.1995.512463

Cited by 8 publications

(1 citation statement)

References 14 publications

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“…It consists of the time needed for building the testbench, the pure simulation time and the time of a turn-around cycle. Corresponding to design, re-use is a key methodology to increase the complexity of testbenches [2], [8], [9], [10]. This methodology can obviously applied to standardized protocol generators 1 , because many designs serves one or more of these protocols.…”

Section: Introductionmentioning

confidence: 99%

Platform-based testbench generation

Henftling¹,

Zinn

Bauer

et al.

2003 Design, Automation and Test in Europe Conference and Exhibition

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This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.

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Section: Introductionmentioning

confidence: 99%