An integrated low power transceiver system

Abstract

In this paper, an integrated transceiver system has been designed and fabricated. The system integrates an OOK receiver, a transmitter, RF/DC switches and a voltage regulator in a 2x2 mm2 chip. A low noise amplifier (LNA) works at sub-threshold range to achieve maximum power efficiency. A Villard voltage doubler circuit have been used to improve the system sensitivity with near zero power consumption. The system obtains a receiver sensitivity of -60 dBm with 4mW @ 1.4 V.