An intelligent readout integrated circuit (iROIC) with on-chip local gradient operations

Sot, Javier E.; Valenzuela, Wladimir E.; Diaz, Silvana; Saavedra, Antonio; Figueroa, Miguel; Ghasemi, Jahan B.; Zarkesh-Ha, Payman

doi:10.1109/icecs.2017.8292082

Cited by 3 publications

(4 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, LBP requires eight comparisons per pixel. In our RLBP method [ 41 ], shown in Figure 2 b, each pixel is compared only to its rightmost neighbor and the results from the comparisons of the eight neighbors are concatenated to build the pattern vector. Unlike LBP, RLBP requires only one comparison per pixel, because the result of each comparison is used in eight different kernels.…”

Section: Methodsmentioning

confidence: 99%

“…Indeed, Gottardi et al [ 52 ] computes the difference between neighboring pixels during integration to obtain a simplified version of LBP. In our own previous work [ 41 ], we propose analog circuits at the pixel level to compute local spatial gradients during integration, which can be used to perform face recognition using external circuitry.…”

Section: Related Workmentioning

confidence: 99%

“…In previous work, we proposed an intelligent readout integrated circuit (iROIC) that computes local gradients on-chip [ 41 ]. This iROIC includes the architecture of an analog smart pixel that can be programmed to compute the local differences between neighbor pixels during integration time.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we present the design and evaluation of a complete SIS architecture based on the algorithm and smart-pixel design in [ 41 ] to perform face recognition during image capture. The proposed SIS design is suitable for mobile devices, where the SIS can be operated as a conventional sensor to capture images of a scene, or as a face recognition system to obtain the identity of a subject.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Face Recognition on a Smart Image Sensor Using Local Gradients

Valenzuela

Soto

Zarkesh-Ha

et al. 2021

Sensors

Self Cite

View full text Add to dashboard Cite

In this paper, we present the architecture of a smart imaging sensor (SIS) for face recognition, based on a custom-design smart pixel capable of computing local spatial gradients in the analog domain, and a digital coprocessor that performs image classification. The SIS uses spatial gradients to compute a lightweight version of local binary patterns (LBP), which we term ringed LBP (RLBP). Our face recognition method, which is based on Ahonen’s algorithm, operates in three stages: (1) it extracts local image features using RLBP, (2) it computes a feature vector using RLBP histograms, (3) it projects the vector onto a subspace that maximizes class separation and classifies the image using a nearest neighbor criterion. We designed the smart pixel using the TSMC 0.35 μm mixed-signal CMOS process, and evaluated its performance using postlayout parasitic extraction. We also designed and implemented the digital coprocessor on a Xilinx XC7Z020 field-programmable gate array. The smart pixel achieves a fill factor of 34% on the 0.35 μm process and 76% on a 0.18 μm process with 32 μm × 32 μm pixels. The pixel array operates at up to 556 frames per second. The digital coprocessor achieves 96.5% classification accuracy on a database of infrared face images, can classify a 150×80-pixel image in 94 μs, and consumes 71 mW of power.

show abstract

Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Face Recognition on a Smart Image Sensor Using Local Gradients

Valenzuela

Soto

Zarkesh-Ha

et al. 2021

Sensors

Self Cite

View full text Add to dashboard Cite

show abstract

Design and Implementation of Integrated Circuits Using Open Source Tools and SKY130 Free PDK

Herman,

Montanares,

Marin

2023

2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)

View full text Add to dashboard Cite

Motion-Based Object Location on a Smart Image Sensor Using On-Pixel Memory

Valenzuela

Saavedra

Zarkesh-Ha

et al. 2022

Sensors

View full text Add to dashboard Cite

Object location is a crucial computer vision method often used as a previous stage to object classification. Object-location algorithms require high computational and memory resources, which poses a difficult challenge for portable and low-power devices, even when the algorithm is implemented using dedicated digital hardware. Moving part of the computation to the imager may reduce the memory requirements of the digital post-processor and exploit the parallelism available in the algorithm. This paper presents the architecture of a Smart Imaging Sensor (SIS) that performs object location using pixel-level parallelism. The SIS is based on a custom smart pixel, capable of computing frame differences in the analog domain, and a digital coprocessor that performs morphological operations and connected components to determine the bounding boxes of the detected objects. The smart-pixel array implements on-pixel temporal difference computation using analog memories to detect motion between consecutive frames. Our SIS can operate in two modes: (1) as a conventional image sensor and (2) as a smart sensor which delivers a binary image that highlights the pixels in which movement is detected between consecutive frames and the object bounding boxes. In this paper, we present the design of the smart pixel and evaluate its performance using post-parasitic extraction on a 0.35 µm mixed-signal CMOS process. With a pixel-pitch of 32 µm × 32 µm, we achieved a fill factor of 28%. To evaluate the scalability of the design, we ported the layout to a 0.18 µm process, achieving a fill factor of 74%. On an array of 320×240 smart pixels, the circuit operates at a maximum frame rate of 3846 frames per second. The digital coprocessor was implemented and validated on a Xilinx Artix-7 XC7A35T field-programmable gate array that runs at 125 MHz, locates objects in a video frame in 0.614 µs, and has a power consumption of 58 mW.

show abstract

An intelligent readout integrated circuit (iROIC) with on-chip local gradient operations

Cited by 3 publications

References 7 publications

Face Recognition on a Smart Image Sensor Using Local Gradients

Face Recognition on a Smart Image Sensor Using Local Gradients

Design and Implementation of Integrated Circuits Using Open Source Tools and SKY130 Free PDK

Motion-Based Object Location on a Smart Image Sensor Using On-Pixel Memory

Contact Info

Product

Resources

About