An On-Chip Clock Generation Circuit for Smart Catheters

Abstract

Cardiovascular diseases are one of the major causes of death worldwide, which drives the research on smart catheters for early diagnosis. Deploying ASICs at the tip of the catheter is challenging, as power is delivered through a long and thin wire, limiting the power integrity. Also, since the catheter needs to fit into the diameter of a blood vessel or other narrow channel in the human body, there is no room for bulky decoupling capacitors. Finally, power consumption must be optimized, as the energy density may lead to prohibitive heating of tissues and fluids. Still, while targeting better performance, e.g. higher imaging resolution, the requirements for bandwidth and accuracy consistently increase, ultimately demanding precise on-chip clock generation for communication and digitization. In this paper we propose a circuit for at-the-tip clock generation in smart catheters, comprising a low-drop out (LDO) regulator, voltage and current references and a low-jitter digitally controlled oscillator (DCO). The clock generator also comprises a clock divider with programmable duty cycle, allowing system reconfiguration. The circuit is laid out and simulated under application conditions. The LDO achieves a full-spectrum power supply ripple rejection (PSRR) of 50 dB with an output load of 10 mA. The DCO, supplied by the aforementioned LDO, achieves a phase noise of -104.5 dBc/Hz at an offset of 1 MHz and 1.25 GHz of oscillating frequency. The proposed clock generator allows digitization at 200 MSps with a maximum SNR of 56.3 dB for an input signal of 50 MHz if phase noise is integrated from 100 kHz to 625 MHz.