An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

Mohr, Bastian; Zimmermann, Niklas; Thiel, Bjoern Thorsten; Mueller, J. Howard; Wang, Yifan; Zhang, Ye; Lemke, Frank; Leys, Richard; Schenk, Sven; Bruening, Ulrich; Negra, Renato; Heinen, Stefan

doi:10.1109/rfic.2012.6242243

Cited by 16 publications

(5 citation statements)

References 8 publications

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“…In the most conventional structure, this is achieved with two digital-to-analog converters (DACs) followed by the required filters and mixers [6][7][8][9]. However, in many recent implementations, these circuits have been replaced by radio-frequency digital-to-analog converters (RF-DACs), which combine the functionality of a DAC and a mixer and enable pushing the digital-to-analog boundary closer to the antenna [10][11][12][13]. A generic, simplified block diagram of an RF-DAC-based Cartesian transmitter is depicted in Figure 2.1.…”

Section: Cartesian Transmittersmentioning

confidence: 99%

Multilevel outphasing power amplifier system with a transmission-line power combiner

Martelius

Stadius

Lemberg

et al. 2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Section: Cartesian Transmittersmentioning

confidence: 99%

Multilevel outphasing power amplifier system with a transmission-line power combiner

Martelius

Stadius

Lemberg

et al. 2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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“…WiMAX, WiFi (2.4 GHz band), UN-II band (5 GHz band) and UWB (3-10 GHz). Instead, nearly "digital" ∆Σ solutions have been proposed wherein the baseband is up-sampled and digitally processed at a higher frequency [8,26,27,30,31] while the mixing is performed in the analog domain as shown in Figs. 1-10 and 1-11.…”

Section: ∆σ Dac Based Transmittersmentioning

confidence: 99%

“…Some examples of these techniques in transmitters include oversampling/interpolation filtering to reduce the anti-aliasing filter order and the use of ∆Σ modulation to reduce the number of DAC unit cells [8,[25][26][27]30]. However, these techniques have been applied only for relatively low channel-bandwidth standards (< 160 MHz) e.g.…”

Section: Introductionmentioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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“…Such signal related to present standards of communications. Many scholars have [14] introduced an RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS" A transmission device which is formed on the basis of high frequency digital to analog converter was put into place for the very first time in this s work. It was put into place for the very first time in the favor of broadcasting cell phones as well as for application related to network within a 65 nano meter complementary metal oxide semiconductor methodology.…”

Section: Introductionmentioning

confidence: 99%

Designing CMOS based Class E Power Amplifier

Anand¹

2019

IJRASET

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Here in this paper the power amplifier and CMOS has been explained. The present researches in sector of power amplifier and CMOS are also discussed here. The proposed work focus on the design and implementation of Class E power amplifier that should be CMOS technology based. The simulation of work is made in MATLAB. The design of circuit has been built of Simulink tool available in MATLAB. The proposed work would play significant role in designing application particular integrated circuits. Multi mode class e radio power amplifier has been using 30 nm CMOS technology with programming. This research has proposed Advanced CMOS RF Power Amplifier Architecture. Research has presented PAE% according to frequency. Comparison chart of Tradition researches where frequency was 5.2 to 13 ghz , 4 to 17 ghz, 6.5 to 13 ghz, 0.1 to 65 ghz,0.2 to 2.5 ghz in proposed research frequency 2.4ghz has been represented. Output power & power gain has been simulated in this section. Multi mode class e radio power amplifier has been using 30 nm CMOS technology with programming. Such system would be suitable for low power fifth generation wireless networks.

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An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

Cited by 16 publications

References 8 publications

Multilevel outphasing power amplifier system with a transmission-line power combiner

Multilevel outphasing power amplifier system with a transmission-line power combiner

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Designing CMOS based Class E Power Amplifier

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