An Ultra-Low-Power and Robust Ternary Static Random Access Memory Cell Based on Carbon Nanotube FETs

Moaiyeri, Mohammad Hossein; Akbari, Hamed; Moghaddam, Majid

doi:10.1166/jno.2018.2145

Cited by 17 publications

(9 citation statements)

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“…This is due to the higher threshold voltage of the binary inverters in the first proposed memory cell (the higher threshold voltage leads to the lower leakage current). Although, as shown in [31], using stacked STIs lead to the considerable reduction of leakage current and direct current, this increases the delay under load for reading delay.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

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Low storage power and high noise margin ternary memory cells in nanoelectronics

Hosseini

Etezadi

2020

IET Circuits, Devices & Systems

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Section: Simulation Results and Comparisonsmentioning

confidence: 99%

“…Moaiyri et al . [31] use the cross‐coupled stacked STIs (cascode) for the ternary latch. This leads to the reduction of static power and also, noise margin improvement; however, there is also the problem of more transistor counts.…”

Section: Related Workmentioning

confidence: 99%

Low storage power and high noise margin ternary memory cells in nanoelectronics

Hosseini

Etezadi

2020

IET Circuits, Devices & Systems

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“…This results in high power consumption. So, new designs for ternary SRAM cells were proposed in litareture [20][21][22] to decrease power consumption in SRAMs.…”

Section: Ternary Sram Cellmentioning

confidence: 99%

CNTFET‐based ternary address decoder design

Mohammed

Fouda

Alouani

et al. 2022

Circuit Theory & Apps

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Summary With the end of Moore's law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power‐ and time‐consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre‐decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs.

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“…There are some examples of ternary inverters with uniform NMs in the literature a well. The VTC curves in [32][33][34][35] are properly shaped. However, the ones in [32][33][34] have more transistors than other well-known competitors.…”

Section: Introductionmentioning

confidence: 99%

“…The VTC curves in [32][33][34][35] are properly shaped. However, the ones in [32][33][34] have more transistors than other well-known competitors. Besides, the structures of [33] and [34] are based on dynamic logic and Differential Cascode Voltage Switch Logic (DCVSL), respectively, whose applications are somehow limited in digital electronics.…”

Section: Introductionmentioning

confidence: 99%

Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

2022

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Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFETbased STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.

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An Ultra-Low-Power and Robust Ternary Static Random Access Memory Cell Based on Carbon Nanotube FETs

Cited by 17 publications

References 0 publications

Low storage power and high noise margin ternary memory cells in nanoelectronics

Low storage power and high noise margin ternary memory cells in nanoelectronics

CNTFET‐based ternary address decoder design

Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

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