An Ultra-Low-Power Successive-Approximation-Based ADC for Implantable Sensing Devices

Robert, Pierre-Yves; Gosselin, Benoît; Ayoub, A.E.

doi:10.1109/mwscas.2006.381981

Cited by 17 publications

(11 citation statements)

References 6 publications

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“…The circuit consumes only 7.4 μW, and its ENOB is 6.5 bits at a sampling frequency of 30 kHz. In addition to being very low‐power, it occupies a very small area and uses a minimum number of matched capacitors . The schematic of this SAR ADC is shown in Figure .…”

Section: Previous Work In Neural Adcsmentioning

confidence: 99%

A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems

Jomehei

Sheikhaei

Saberi

2020

Circuit Theory & Apps

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Summary A digital‐ramp hybrid exponential‐linear analog‐to‐digital converter (ADC) is presented in this paper, which is attractive, where a high dynamic range (DR) is required. It is especially applicable for sampling neural (bio‐potential) signals, as most of the neural signal data are concentrated on higher side of the amplitude range. By the exponential quantization function for low signal amplitudes, the background noise that disperses in lower amplitudes will be reduced. For higher signal amplitudes, the exponential function optionally switches to linear function at an adjustable voltage threshold, to reduce required number of bits for those high amplitudes, as well. As a result of this exponential‐linear hybrid operation, the total data rate and the power required for data transmission are decreased. A prototype 8‐bit counter‐based exponential ADC is designed and simulated in 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS). The 20‐KS/s ADC achieves a DR of 66 dB, occupies 0.036 mm2 area, and consumes 6.4‐μW power from a 1.8‐V supply. Integral nonlinearity (INL) and differential nonlinearity (DNL) that are redefined to be compatible with nonlinear ADCs are 3.2 and 0.88 least significant bits (LSBs), respectively.

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Section: Previous Work In Neural Adcsmentioning

confidence: 99%

A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems

Jomehei

Sheikhaei

Saberi

2020

Circuit Theory & Apps

View full text Add to dashboard Cite

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“…The output of the neural signal conditioning stage is digitized by a successive-approximation (SA)-based ADC (presented in [10]), the block diagram of which is shown on the right hand side in Fig. 2.…”

Section: Digitization and Data Readoutmentioning

confidence: 99%

A low-power integrated neural interface with digital spike detection and extraction

Gosselin

2009

Analog Integr Circ Sig Process

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We present the design of an integrated neural interface intended for multi-channel neural recording. The design features a mixed-signal part that handles neural signal conditioning, digitization, time-division multiplexing, and a digital module providing control, absolute threshold detection, extraction of spikes, and serial communications towards a host interface. The detection and extraction strategy preserves the entire neuronal spike waveshapes by means of synchronized internal data buffering. This bandwidth reduction scheme prompts for better waveform sorting results and improved performance in prosthetic applications. Both parts of the presented neural interface were fabricated separately in a CMOS 0.18 lm process. The whole neural interface features 16 channels for validation, but, the proposed approach is scalable to larger channel counts. The performance of the implemented neural interface was validated on testbench with synthetic neural waveforms. It features a power consumption of 138 lW per channel and a size of 2.304 mm 2 , and achieves a bandwidth reduction factor of up to 48.

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“…The output of the neural signal conditioning stage is digitized by a successive-approximation (SA)-based ADC (presented in [7]) which block diagram in shown in Fig. 5.…”

Section: Digitization and Digital Readoutmentioning

confidence: 99%

A Mixed-Signal Multi-Chip Neural Recording Interface with Bandwidth Reduction

Gosselin

Ayoub

2007

2007 IEEE Biomedical Circuits and Systems Conference

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We present the design of a multi-chip neural interface intended for multi-channel neural recording. The design features a mixed-signal part that handles neural signal conditioning, digitization and time-division multiplexing, and a digital part that provides control, bandwidth reduction, and serial communications towards a host interface. The two CMOS 0.18-μm fabricated embedded circuits that implement both parts are directly mounted on the back of a medical-grade stainless steel microelectrodes array and wire-bonded to its post-processed base. The presented neural interface integrates 16 channels for validation; however, the proposed approach is scalable to larger channel counts. In fact, it is suitable to implement microsystems including several hundreds of recording channels. The performance of the implemented multi-channel interface was validated with real neural waveforms.

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An Ultra-Low-Power Successive-Approximation-Based ADC for Implantable Sensing Devices

Cited by 17 publications

References 6 publications

A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems

A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems

A low-power integrated neural interface with digital spike detection and extraction

A Mixed-Signal Multi-Chip Neural Recording Interface with Bandwidth Reduction

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