Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

Abstract

We report a systematic, quantitative investigation of analog and RF performance of cylindrical surroundinggate (SRG) silicon MOSFET. To derive the model, a pseudotwo-dimensional (2-D) approach applying Gauss's law in the channel region is extended for the cylindrical SRG MOSFET. Based on surface potential approach, expressions of drain current and differential capacitances are obtained analytically. Analog/RF figures of merit of SRG MOSFET are studied, including transconductance efficiency g m /I d , intrinsic gain, output resistance, cutoff frequency f T , maximum oscillation frequency f max and gain bandwidth product GBW. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modeled predictions have been extensively compared with the simulated characteristics obtained from the ATLAS device simulator and a nice agreement is observed with a wide range of geometrical parameters.

Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

“…A parameter generally described when comparing transistors for RF applications is the cut-off frequency, f T [31,32]. f T is a specification for high-speed digital applications (speed and high swing) and can be defined as follow:…”

Numerical modeling on the optical characteristics of triple material gate stack gate all-around (TMGSGAA) MOSFET

“…The results are then substituted in above equations where current is expressed in terms of carrier density, which is continuous from subthreshold to strong inversion region. The transconductance g m is expressed as [11] …”

“…where l 0 is electron mobility with its value taken to be 677 cm 2 /V s, the values of the parameters S = 350, N ref = 3 Â 10 22 m À3 and high field saturation velocity V sat = 10 7 cm/s is considered as given in [11] The expressions for the terminal charges were derived using the Ward-Dutton linear charge partition method [11].…”

“…The implementation of high-k dielectrics in the gate all-around MOSFETs leads to an improvement of subthreshold behavior and hot-carrier immunity while enhancing the gate controllability, and thus provides better performance as compared to conventional GAA MOSFETs [10]. Sarkar et al [11] reported a systematic, quantitative investigation of analog and RF performance of cylindrical surrounding gate (SRG) silicon MOSFET. To derive the model, a pseudo two-dimensional (2-D) approach applying Gauss's law in the channel region is extended for the cylindrical SRG MOSFET.…”

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

“…In addition, the radius of the nanowire can readily be reduced to a few nanometres in size that limits the scaling of conventional MOSFET and also because of their adoptability for high-density integration including that of 3D [7,8]. It was also found that gate-all-around (GAA) silicon nanowire transistors (SiNWTs) have cut-off frequency larger than that of planar Si MOSFET [9][10][11]. However, as with many novel device architectures, the SiNW MOSFET has problems of its own.…”