Analog Domain Carrier Phase Synchronization in Coherent Homodyne Data Center Interconnects

Ashok, Rakesh; Naaz, Sana; Kamran, Rashmi; Gupta, Shalabh

doi:10.1109/jlt.2021.3096605

Cited by 18 publications

(13 citation statements)

References 31 publications

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“…1. A generic ASP receiver architecture for polarization division multiplexed system with laser phase/frequency offset is detailed in [1,5]. The modulated signal (S) and unmodulated carrier (LO) from the received signal are separated with the aid of an adaptive polarization controller consisting of an electronic polarization controller, polarization beam splitter, power splitter, photodetector, and adaptative polarization control circuit [14].…”

Section: System Design and Overviewmentioning

confidence: 99%

“…However, the severity of the impairments introduced in the DCIs is not as significant as that in the long-haul links. Therefore, the power hungry data conversion and digital signal processing based approach can be avoided and substituted by optical domain processing and analog signal processing (ASP) for considerable power, complexity, form-factor, and latency reduction [5]. The enhanced energy efficiency and reduced complexity in the ASP approach are attributed to the omission of analog to digital converters (ADCs) and massive number of operations in digital signal processors (DSPs).…”

Section: Introductionmentioning

confidence: 99%

“…The enhanced energy efficiency and reduced complexity in the ASP approach are attributed to the omission of analog to digital converters (ADCs) and massive number of operations in digital signal processors (DSPs). In the literature, all-analog coherent receiver solutions compensating for dispersion and laser offsets are presented in [1,3,[5][6][7]. When projected to the 400ZR standard, the ASP approach implemented in a 7 nm FinFET technology can save ∼3.6 W compared to its digital counterpart [5].…”

Section: Introductionmentioning

confidence: 99%

“…In the literature, all-analog coherent receiver solutions compensating for dispersion and laser offsets are presented in [1,3,[5][6][7]. When projected to the 400ZR standard, the ASP approach implemented in a 7 nm FinFET technology can save ∼3.6 W compared to its digital counterpart [5].…”

Section: Introductionmentioning

confidence: 99%

“…This work presents the demonstration of a SiPIC integrated coherent receiver (ICR) in a Costas loop with carrier phase recovery (CPR) chip (the stand-alone CPR chip has been presented earlier in [5]). Functional validation of the EIC-PIC receiver has been performed for the QPSK homodyne link.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

An Analog Signal Processing EIC-PIC Solution for Coherent Data Center Interconnects

Chugh¹,

Ashok²,

Jain³

et al. 2022

Preprint

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Data center interconnects (DCIs) will have to support throughputs of 400 Gbps or more per wavelength in the near future. To achieve such high data rates, coherent modulation and detection is used, which conventionally requires high-speed data conversion and signal processing in the digital domain. Alternatively, high-speed signal conditioning and processing could be carried out in co-designed photonic and electronic integrated circuits, in the optical and electrical analog domains, respectively, to achieve reduced power consumption, latency, form factor, and cost. A few demonstrations of analog domain processing electronic integrated circuits (EICs), including those of equalizer and carrier phase recovery (CPR) modules showcase progress in this direction in the literature. In this brief, for the first time, we present integration of a silicon photonic integrated coherent receiver (ICR) module with a CPR module, as a part of a complete coherent receiver solution. A phase shifter in the ICR (fabricated in a 220 nm silicon-on-insulator technology) receives feedback from a CPR EIC, and the combination compensates for the time varying phase offset between the modulated signal and the unmodulated carrier in the closed loop configuration. In this proof-of-concept demonstration, we present experimental results obtained from the stand-alone silicon photonic ICR along with its system level integration with CPR chip, for QPSK signals. The technique can be extended to a higher-order modulation format, such as 16-QAM, for data rate scaling. The proposed scheme is suitable for homodyne systems, such as polarization multiplexed carrier based self-homodyne links.

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Section: System Design and Overviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%