Analysis and Design of a New 10-Bit High Accuracy and Resolution TDC by Elimination of Offset Voltage and Parasitic Capacitors Effects

Abstract

This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and usage of the analog interpolation structure. Moreover, it does not use gated delay lines in its structure and has the advantage of low sensitivity to the temperature, power supply and process (PVT) variations. For validation, the proposed TDC is designed in TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology and simulated by Hspice simulator. The comparison between the theoretical and simulation results confirms the benefits of the proposed TDC operation. The results prove that it can be employed for high speed and resolution applications.