Analysis and Design of Capacitive DAC Array Switching Scheme for SAR ADC in Low Power Applications

Abstract

Successive-approximation ADCs (SA-ADCs) have found a wide range of applications requiring low speed and moderate resolution, very-high speed and low resolution or even high speed and high resolution Low-power SA-ADCs have been widely used in low-speed biomedical applications with a limited power budget.Several attempts have been reported in order to reduce the power consumption of the ADC with an emphasis on the employed capacitive DAC. In this paper, both the capacitive digital-to-analog converter (DAC) and the comparator are modified from the typical structure. The conventional structure of an SA-ADC, consists of a sample-and-hold (S/H) circuit, a comparator, a successive approximation register (SAR), and a digital-to-analog converter (DAC).Among them DAC has greater importance, which consumes major power in the ADC module.So by careful designing of DAC module its possible to reduce the power consumption to a great extend. By modifying the existing Conventional DAC architecture, ,its found that the power consumption of the DAC is significantly reduced.In the exsiting Conventional DAC power consumption is found to be about 12mW. But in modified architecture power consumption is reduced to 7mW.So it is stated that by using modified DAC module its possible to work the ADC in low power applications