Analysis and Design of Low-Complexity Stochastic DEM Encoder for Reduced-Distortion Multi-bit DAC in Sigma-Delta Modulators

Li, Di; Fei, Chunlong; Zhang, Qidong

doi:10.1007/s00034-020-01470-2

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Analysis and Design of Low-Complexity Stochastic DEM Encoder for Reduced-Distortion Multi-bit DAC in Sigma-Delta Modulators

Cited by 4 publications

References 26 publications

Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA

Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA

A low-power sigma-delta modulator based on high-order op-amp sharing technique for speech communication

A 16-bit DPT-DAC over 120dBc SFDR with Signal-Phase regulation and Switching-Glitch neutralization

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