Analysis and design of voltage‐source parallel resonant class E frequency multiplier

Abstract

In this paper, the analysis and design process of the voltage‐source parallel resonant class E frequency multiplier with a 50% duty ratio is proposed. The proposed circuit adopts two series resonant filters for reducing the interference of harmonics to the output waveform and achieves zero‐voltage switching (ZVS) and zero‐voltage derivation switching (ZVDS) conditions. The design equations for the proposed circuit are given in detail. The new type class E frequency multiplier can operate at lower transistor voltage stress, higher operating frequency, and larger output power. Meanwhile, the volume and weight of the measured circuit are greatly decreased compared to the conventional class E frequency multiplier. To demonstrate the analysis process, the circuit operating at 1 MHz is fabricated and measured. Compared to the traditional class E frequency multiplier, the transistor peak voltage is reduced by 47.9%, the diameter of the resonant inductor core is decreased by 56.2%, and the measured efficiency can reach 95.1%. The theoretical and simulated results are all agreed with the experimental results.