Analysis and Equalization of Data-Dependent Jitter

Abstract

Abstract-Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase-and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10 12 BER from 30 to 52 ps at 10 Gb/s.

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

“…13 at 6 Gb/s. The DDJ component is normalized out of this total jitter and the time delay compensation can be caculated from the DDJ peak separation [5]. The linearity of the time delay compensation is assessed from the slope of this curve as a function of the digital code.…”

“…If we assume that the channel is linear, the timing deviation of complementary signals, i.e., a 101 and 010 data sequences, is identical. In [5], we demonstrated the adjustment of the data transition timing at the receiver to compensate for the effect of DDJ. This work focuses on DDJ compensation in the transmitter where there are several implementation advantages.…”

“…The detection of th previous transition is denoted for the current bit, , and is calculated from , where is the XOR operator. From derivations in [5], the compensated transmit time is calculated through the following algorithm: (5) For example, the 0010 sequence results in the fastest threshold crossing time for a first-order system. For this sequence, and are both 1, implying that we will introduce the largest delay to compensate the fast transition for this sequence.…”

“…DDJ compensation has been demonstrated to increase the timing margins in clock and data recovery [4], [5]. Unlike random jitter (RJ), DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation [6], [7].…”

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

“…Previous works [7] derive the relationship between the zero crossing and the channel intersymbol interference (ISI) in the form of equations using a linearized clock-and-data recovery (CDR) model and frequency-domain analysis. This approach, however, does not apply to the nonlinear behavior of bang-bang [8] simulations.…”