Analysis, Design and Optimization of Active Devices

Guerra-Gomez, I.; Tlelo‐Cuautle, Esteban; Duarte-Villaseñor, Miguel Aurelio; Sánchez–López, C.

doi:10.1007/978-1-4614-1383-7_1

Cited by 2 publications

(5 citation statements)

References 33 publications

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“…The first step divides the entire search space into two parts corresponding to the two first levels (level 0 and level 1) that share an intersection region to relax the partitioning, and allowing exploring beyond the bound limits. The intersection between two levels () depends on the total number of levels and is controlled by using an integer scaling factor (), as shown by (1). Since TL > 0 and  > 0, then  < 0.5.…”

Section: Topological Circuit Analysismentioning

confidence: 99%

“…Among the many available active devices [1], [5], [10], [20], [21], our CBBA approach is tested by optimizing the recycled folded cascode (RFC) operational transconductance amplifier (OTA) shown in Fig. 2.…”

Section: Application Examplementioning

confidence: 99%

“…Is for that reason that we apply heuristics herein for optimizing its performances, but the main goal is focused on showing that by applying our proposed CBBA approach, the execution of the three evolutionary algorithms (EAs): NSGA-II [13], MOEA/D [14] and MOPSO [15], is being improved and accelerated. The implementation details of those three EAs when applied to the optimal sizing of analog ICs can be found in [1], [2], [4], [6]. The inclusion of our proposed CBBA approach is straightforward but quite useful.…”

Section: Application Examplementioning

confidence: 99%

“…The sizing optimization of analog integrated circuits (ICs) by applying heuristic approaches has grown in the last decade [1]- [8]. For instance, evolutionary algorithms (EAs) are preferred because they provide a set of feasible solutions [4].…”

Section: Introductionmentioning

confidence: 99%

“…The usefulness of our proposed CBBA approach is demonstrated by sizing the recycled folded cascode (RFC) operational transconductance amplifier (OTA) given in [9], by applying three EAs, namely: non-dominated sorting genetic algorithm (NSGA-II) [13], multi-objective EA with decomposition (MOEA/D) [14], and multi-objective particle swarm optimization (MOPSO) [15]. These EAs have been applied to sizing analog ICs in [1], [2], [4], [6]. In those references one can find their implementation details, and one can infer that at this moment any EA considers CBBA before starting the sizing optimization process.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Sizing Analog Integrated Circuits by Current-Branches-Bias Assignments with Heuristics

Guerra-Gomez

Tlelo‐Cuautle

2013

ElAEE

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This work shows the usefulness of assigning current-branches-bias levels, in order to improve and accelerate the sizing optimization of MOSFET-based analog integrated circuits (ICs). That way, the proposed procedure relies on the search of current branches from the associated incidence matrix by applying a recursive technique for exploring circuit graphs. The goal is focused on determining the bounds of the width/length (W/L) search space for each MOSFET before starting the sizing optimization process. As a case of study, the proposed current-branches-bias assignment (CBBA) approach is applied in the sizing optimization of the recycled folded cascode operational transconductance amplifier by applying evolutionary algorithms (EAs). From the feasible optimization results, we conclude that our proposed CBBA approach enhances and accelerates the biasing and sizing of analog ICs by EAs.

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Section: Topological Circuit Analysismentioning

confidence: 99%