Analysis of Error Masking and Restoring Properties of Sequential Circuits

Liang, Jinghang; Han, Jie; Lombardi, Fabrizio

doi:10.1109/tc.2012.147

Cited by 8 publications

(2 citation statements)

References 27 publications

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“…The work in [18] analyses error masking in sequential circuits based on identifying restoring inputs. Restoring inputs allow for the masking of feedback signals, and eliminate the cumulative effect of errors.…”

Section: B Synthesis-based Techniquesmentioning

confidence: 99%

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

El-Maleh

Daud

2015

IEEE Trans. Rel.

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Due to current technology scaling trends, digital designs are becoming more sensitive to radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low-energy particle can flip the output of a gate, resulting in a soft error if it propagates to a circuit output. Thus, soft error tolerance has become an important criterion in digital system design. In this work, we propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed method is based on maximizing the probability of logical masking when a soft error occurs. This maximization is done by extracting sub-circuits from an original multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against a single fault. We present a two-level synthesis scheme to maximize soft error masking on each extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a probability of circuit failure reduction of 32% is achieved compared to the original circuit. The average area overhead is 40% of the original circuit. Index Terms-Combinationalcircuit reliability, fault tolerance, single event transient, single event upset, soft errors. ACRONYMS AND ABBREVIATIONS SET single-event transient SEU single-event upset FX fast extraction CMOS complementary metal oxide semiconductor SER soft error rate TMR triple modular redundancy HICC history index of correct computation CDC controllability don't-care condition Vdd voltage drain-to-drain GND ground Manuscript

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Section: B Synthesis-based Techniquesmentioning

confidence: 99%

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

El-Maleh

Daud

2015

IEEE Trans. Rel.

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“…However, both approaches do not provide protection for errors occurring in the combinational logic of outputs. The work in [12] assigns do not‐care values during logic synthesis into restoring inputs such that errors in the state variables can be corrected during normal operation. In [13], an FSM‐based fault tolerance technique has been proposed.…”

Section: Introductionmentioning

confidence: 99%

Finite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits

El‐Maleh

2017

IET Computers & Digital Techniques

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Recently, a finite state machine-based fault tolerance technique for sequential circuits based on protecting few states with high probability of occurrence has been proposed. In this study, the authors propose an algorithm that starts with a given state assignment targeting the optimisation of either area or power and generates a state assignment that preserves the original state assignment and satisfies the fault tolerance requirements for the protected states. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesised sequential circuits while enhancing their fault tolerance.

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Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths

2015

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Analysis of Error Masking and Restoring Properties of Sequential Circuits

Cited by 8 publications

References 27 publications

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

Finite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits

Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths

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