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The theoretical propositions of the algebra of logic are considered. It is noted that the current microcircuitry based on the algebra of logic contains logical statements: true (yes) is a logical unit, false (no) is a logical zero. Based on the given logical function: ((ABC)×D + A×(BCD) + A×(BC)×D + (AB)×(CD), frontal, minimal, transformed minimal variants of the combination device are implemented, as well as minimized variants in the bases "AND-NOT" and "OR-NOT". A combination device based on import-substituting chips of 155, 176 series has been designed. The analysis of the obtained devices is made from the standpoint of technical and economic indicators, in particular, an assessment of the number of logic elements used, an assessment of the symmetry of the structure, as a result, a reduction in energy consumption, an increase in performance, improvements in parameters for reliability of functioning, a decrease in weight and size characteristics. Assuming that the law of change of the information parameter U1 is close to linear, taking into account the effect of temperature as boundary values for the elements of the applied microcircuits, taking the values -60 °C and +120°. Accordingly, the parametric reliability of the optimal implementation of the device according to the output voltage parameter is calculated. The conclusion is made about the inverse dependence of parametric reliability on temperature growth. A recommendation is given when evaluating parametric reliability for a number of other information parameters about the need to take into account both the number of chips used and the type of their interconnections.
The theoretical propositions of the algebra of logic are considered. It is noted that the current microcircuitry based on the algebra of logic contains logical statements: true (yes) is a logical unit, false (no) is a logical zero. Based on the given logical function: ((ABC)×D + A×(BCD) + A×(BC)×D + (AB)×(CD), frontal, minimal, transformed minimal variants of the combination device are implemented, as well as minimized variants in the bases "AND-NOT" and "OR-NOT". A combination device based on import-substituting chips of 155, 176 series has been designed. The analysis of the obtained devices is made from the standpoint of technical and economic indicators, in particular, an assessment of the number of logic elements used, an assessment of the symmetry of the structure, as a result, a reduction in energy consumption, an increase in performance, improvements in parameters for reliability of functioning, a decrease in weight and size characteristics. Assuming that the law of change of the information parameter U1 is close to linear, taking into account the effect of temperature as boundary values for the elements of the applied microcircuits, taking the values -60 °C and +120°. Accordingly, the parametric reliability of the optimal implementation of the device according to the output voltage parameter is calculated. The conclusion is made about the inverse dependence of parametric reliability on temperature growth. A recommendation is given when evaluating parametric reliability for a number of other information parameters about the need to take into account both the number of chips used and the type of their interconnections.
The fundamental laws of the positive algebra of logic are considered, including the rules relating to the elements of equivalence and non-equivalence. Logic gates used in practice are presented. The whole set of standard schemes is implemented, in particular, the frontal version, minimized, in the "OR–NOT" basis, in the "AND–NOT" basis based on the initial logical dependence: ¬(¬(A¬B) × ¬(¬CD) + ¬(¬AB) × ¬(C¬D)) + ¬(¬(AB) × ¬(CD) + ¬(¬A¬B) × ¬(¬C¬D)) . A combination device based on K176LE5 chips has been designed. It is noted that the implementation of this function requires at least 3 chips in the Pier basis, which is not optimal in terms of reliability and weight and size indicators. The transition from the minimized variant to the basis of "Non-Equivalence" + "Conjunction", as well as the basis of "Equivalence" + "Pierce function" is carried out. The results of the search for existing chips that implement the functions "Exclusive OR", "AND", "Exclusive OR–NOT" and "OR-NOT" are presented. 4 groups of chips were found, such as: chips based on logic with emitter coupling (ECL), based on transistor-transistor logic (TTL), based on a series of CMOS chips: with a supply voltage of 5-15 V, and also with a supply voltage of 3-5 V. The corresponding descriptions of each of the MC10H1xx chips (group 1 series); K155xx, xx74xx (group 2 series); K561xx, CD40xxxx (group 3 series); SN74LVCxxx (group 4 series) are presented. Implementation options for these groups of chips in both bases are presented. The cost analysis of the applied microcircuits is made. The calculation of the final cost of products is presented. The conclusion is made about the expediency of using one or another group of microcircuits, depending on the initial requirements set.
The technology of modeling a field-effect transistor in the CAD system COMSOL Multiphysics is considered. The possibilities of CAD, its methods of graphical construction of the model and methods of modeling the behavior of the model are being studied. The object of study is the MOS transistor, its scope, operation and a mathematical model that can be used in designing its operation. The Shikhman-Hodges model, input and output parameters are determined, the degree of its adequacy to a real transistor is set, the main parameters are determined, with the help of which it is possible to conduct a study of a field-effect transistor, its current-voltage characteristic. A transistor model is built in the mode of operation in the mode of small-signal amplifiers, replacing it with a linear four-port model, it is described when this model can be applied when simulating the operation of the device.
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