Analysis of hot-carrier-induced degradation and snapback in submicron 50 V lateral MOS transistors

Ludikhuize, A.W.; Slotboom, M.; Nezar, A.; Nowlin, N.; Brock, Reinhard

doi:10.1109/ispsd.1997.601430

Cited by 23 publications

(6 citation statements)

References 2 publications

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“…This requires the graded drain doping to be low. This device differs from those used in previous high-voltage MOS (HV-MOS) and laterally diffused MOS (LDMOS) studies [1]- [8], most particularly in t OX .…”

Section: Device Descriptionmentioning

confidence: 99%

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Investigation of High-Voltage MOSFET Reliability in $I_{\rm KIRK}$ Region

O'Donovan

Deignan

Moloney

et al. 2007

IEEE Trans. Device Mater. Relib.

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This paper evaluates the hot-carrier performance of the n-channel high-voltage (30 V) MOSFET device. This device is widely used in high-voltage linear products. It can withstand 30 V across any two terminals. This large voltage range requires thorough hot-carrier analysis, investigating potential hot-carrier mechanisms not believed to have been previously explored in the literature. It is established that two different hot-carrier generation mechanisms are occurring: one at I SUB(max) and another at I KIRK . These are investigated through combined device parametric, technology computer-aided design (TCAD) simulation, and hot-carrier reliability data.Index Terms-Degradation mechanism, device optimization, hot carrier. I. DEVICE DESCRIPTIONI N THIS PAPER, we consider a 30-V double diffused drain CMOS integrated into an existing 5-V CMOS process. A schematic of this device is shown in Fig. 1. It features V TH = 1.2 V, L = 6.0 µm, and t OX = 800 A. The lightly doped drain overlaps the gate poly by 1 µm, and the heavily doped contact region is spaced 1.1 µm from the poly edge. For compatibility with the 5-V CMOS, the lightly doped drain is quite shallow, i.e., Xj < 1 µm. For analog circuits, high output resistance and, hence, low I SUB are desirable. This requires the graded drain doping to be low. This device differs from those used in previous high-voltage MOS (HV-MOS) and laterally diffused MOS (LDMOS) studies [1]-[8], most particularly in t OX . II. DEVICE CHARACTERIZATIONParametric analysis produces a substrate current I SUB characteristic at stress V D = 36 V, as shown in Fig. 2. Both ON-state and OFF-state breakdown voltages are > 40 V. The normal I SUB(max) is observed at V G = 8 V and is labeled as "A". An unexpected exponential increase in I SUB is noted in region "B" and is referred to as I KIRK due to its high drain current and low graded drain doping origin [8]- [10].From simulation, shown in Fig. 3, the generated substrate current in region A is the hole current from impact ionization (II) at the drain region under that gate, i.e., a regular MOSFET hot-carrier phenomenon. This II is subsurface and is a distance from the vertical electric field. Fig. 1. Cross section schematic of the 30-V nMOSFET.Fig. 2. Substrate current I SUB characteristic at V D = 36 V.Fig. 3. Region of II by the drain (A) at V D = 30 V and V G = 8 V.of II from the channel region differs from the submicrometer MOSFET situation.The generated substrate current in region B increases with both increasing V D and V G . Simulation shows that this hole current originates from a region of II at the drain contact, as shown in Fig. 4. The transition from graded drain to heavily doped drain causes a large lateral electric field that results in II. This II is a distance from the intrinsic region of the device.1530-4388/$25.00

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Section: Device Descriptionmentioning

confidence: 99%

“…Both ON-state and OFF-state breakdown voltages are > 40 V. The normal I SUB(max) is observed at V G = 8 V and is labeled as "A". An unexpected exponential increase in I SUB is noted in region "B" and is referred to as I KIRK due to its high drain current and low graded drain doping origin [8]- [10].…”

Section: Device Characterizationmentioning

confidence: 99%

Investigation of High-Voltage MOSFET Reliability in $I_{\rm KIRK}$ Region

O'Donovan

Deignan

Moloney

et al. 2007

IEEE Trans. Device Mater. Relib.

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“…Hot-carrier degradation (HCD) still remains one of the main reliability concerns in these devices [1], [2], [3], [4]. This makes a predictive physical model for HCD in LDMOS very attractive.…”

Section: Introductionmentioning

confidence: 99%

Physical modeling of hot-carrier degradation in nLDMOS transistors

Wimmer¹,

Tyaginov

Rudolf

et al. 2014

2014 IEEE International Integrated Reliability Workshop Final Report (IIRW)

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Our physics-based HCD model has been validated using scaled CMOS transistors in our previous work. In this work we apply this model for the first time to a high-voltage nLDMOS device. For the calculation of the degrading behaviour the Boltzmann transport equation solver ViennaSHE is used which also requires high quality adaptive meshing. We discuss the influence of the different model components in the different device regions. Finally we compare the model to experimental degradation results and show that each one gives a significant contribution to the result and that all of them are needed in order to satisfactorily fit the experimental data. I. INTRODUCTIONThe LDMOS transistor is one of the most popular devices employed in mixed-signal integrated circuits and in highvoltage automotive applications [1]. Hot-carrier degradation (HCD) still remains one of the main reliability concerns in these devices [1], [2], [3], [4]. This makes a predictive physical model for HCD in LDMOS very attractive. At the same time, such a model is extremely challenging to develop because of the complexity of the HCD-phenomenon and the complicated topological structure of the LDMOS.In fact, the physical origin of HCD is related to the generation of traps at or near the Si/SiO 2 interface. This generation is due to hot and cold carriers triggering singlecarrier and multiple-carrier dissociation mechanisms [5], [6], [7]. Thus, the key information needed for proper HCD modeling is the carrier energy distribution functions (DFs), which determine the rates of both aforementioned processes. This information can be obtained from a solution of the Boltzmann transport equation (BTE) [5]. Such a solution is challenging even for planar CMOS devices with a simpler architecture and becomes extremely demanding for such devices as the LDMOS transistor. This device has a non-planar interface with a non-trivial distribution of the electric field near the bird's beak (see Figs. 1,3), where the impact ionization spot, and hence the hot-carrier degradation spot are located [3], [4].In this work we apply our physics-based HCD modelwhich has been validated using scaled CMOS transistors with a gate length as short as 65 nm [6], [7] -to represent the linear drain current change due to HCD in a high-voltage device, i.e. the nLDMOS, for the first time.

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“…Therefore, the gate can be directly controlled with 5V signals. A maximum of 180 jNpm can be delivered with a limitation at high drain-source voltages due to the Kirk effect [3]. Figure 6 shows the I-V characteristics of the thin and thick gate oxide EPMOS transistors.…”

Section: D-enmos and Epmos Transistorsmentioning

confidence: 99%

A submicron Bi-CMOS-DMOS process for 20-30 and 50 V applications

Nezar

Ludikhuize²,

Brock³

et al.

Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's

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This paper describes a high voltage process using 0.8 p technology for mixed signal applications. The technology allows the integration of high side 20, 30 and 50-V n-type LDMOS transistors and 50V p-type LDMOS transistor along with dense logic 1 analog 5V-CMOS and complementary low and high voltage bipolar transistors. Extended drain NMOS and PMOS transistors (ENMOS-EPMOS) whose safe operating areas exceed 50V were also implemented. This technology is ideal for intelligent power application.

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Analysis of hot-carrier-induced degradation and snapback in submicron 50 V lateral MOS transistors

Cited by 23 publications

References 2 publications

Investigation of High-Voltage MOSFET Reliability in $I_{\rm KIRK}$ Region

Investigation of High-Voltage MOSFET Reliability in $I_{\rm KIRK}$ Region

Physical modeling of hot-carrier degradation in nLDMOS transistors

A submicron Bi-CMOS-DMOS process for 20-30 and 50 V applications

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