Analysis of Layout-Based RHBD Techniques

Abstract

Radiation hardening techniques play a pivotal role in enhancing the resilience of VLSI circuits employed in radiation environments, most notably in critical applications such as in space technologies. Building upon the preceding chapter, some Radiation Hardening by Design (RHBD) techniques have been devised to effectively counteract the detrimental impact of radiation on electronic circuits, addressing diverse levels of abstraction ranging from circuit layout to system and software design. This chapter delves into an insightful analysis of the efficacy achieved through layout design techniques, namely Gate Sizing (GS), Transistor Stacking (TS), and Transistor Folding (TF). Moreover, it explores the utilization of asymmetric designs and the innovative Diffusion Splitting (DS) technique as means to augment the hardening efficiency while mitigating the associated area overhead.