Analysis of power for double-tail current dynamic latch comparator

Savani, Vijay; Devashrayee, N. M.

doi:10.1007/s10470-019-01472-4

Cited by 10 publications

(1 citation statement)

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“…Several performance parameters can be defined to characterize the latched comparator, and they mostly concern its resolution, speed and energy consumption. The clock-to-output propagation time is defined as the comparator delay [16,[58][59][60]: it measures the time that intercurs from the latching edge of the clock signal to the time when the output voltage can be identified as one of the logic levels (50% of the transition). The comparator delay sets the maximum speed of the comparator.…”

Section: Latched Comparators: Performance Parameters and Application ...mentioning

confidence: 99%

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

Della Sala,

Centurelli,

Scotti

et al. 2023

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This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.

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Section: Latched Comparators: Performance Parameters and Application ...mentioning

confidence: 99%