Analytical Router Modeling for Networks-on-Chip Performance Analysis

Ogras,; Mărculescu, Radu

doi:10.1109/date.2007.364440

Cited by 77 publications

(67 citation statements)

References 13 publications

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“…A model has been developed to capture spatial and temporal characteristics of traffic for regular, homogeneous NoCs [21]. A generalized analytic router model was developed in [22]. It provides detailed statistics during expected traffic, and is applicable to heterogeneous, irregular networks, but relies on the Poisson arrival process and a synchronously-clocked router.…”

Section: Related Workmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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Abstract-Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous networkon-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires.

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Section: Related Workmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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“…In similar, switching in NoC architecture also consider for low power and high speed. A well-known, wormhole switching is proposed in [6]. Routing is considered as the final protocol in NoC architecture.…”

Section: Related Workmentioning

confidence: 99%

Modified TACIT algorithm based on 4H-key distribution for secure routing in NoC architecture

Ambashanker

Kumar

2014

IEICE Electron. Express

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The shortcoming of conventional bus architecture has been overcome by adopting Network on Chip (NoC) in multi core System on Chip (SoC). Many works have been anticipated for NoC, based on network topology, switching methodology and routing techniques. This paper proposes a Modified TACIT algorithm for secure routing in NoC architectures. The key generation is based on four types of HASH function (4H-key) that find hard hitting to the intruder. The algorithm is realized under various block sizes as the 8-bit, 64-bit and 128-bit. The device utilization of the proposed algorithm is determined and the results show that, the maximum frequency achieved by the proposed algorithm (for 8-bit block size) is 640.968 MHz with the total memory usage of 78045 Kb.

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“…The switch model described by Equation (2) provides a closed form expression for the average number of packets at each input port of the switch i, given the traffic arrival rate (Λ), the packet contention probabilities (C), switch design specifications (H, W ) and packet size S. For further details, the reader is referred to [27].…”

Section: B Analytical Switch Modeling For Nocsmentioning

confidence: 99%

“…We utilize the analytical delay model presented in [27], which includes the effects of queueing delay and network contention. The model considers first-come-first-serve input buffered switches and targets wormhole flow control under deterministic routing algorithms.…”

Section: B Analytical Switch Modeling For Nocsmentioning

confidence: 99%

Application-specific 3D Network-on-Chip design using simulated allocation

Zhou¹,

Yuh²,

Sapatnekar³

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplanaware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).

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Analytical Router Modeling for Networks-on-Chip Performance Analysis

Cited by 77 publications

References 13 publications

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Modified TACIT algorithm based on 4H-key distribution for secure routing in NoC architecture

Application-specific 3D Network-on-Chip design using simulated allocation

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