Application of automated topography focus corrections for volume manufacturing

Wiltshire, Timothy J.; Liegl, Bernhard; Hwang, Emily; Lucksinger, Mark R.

doi:10.1117/12.846652

Cited by 2 publications

(1 citation statement)

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“…However, they are suffering performance degradation as they are difficult to take a truly detection of "top surface". The irregularities on the surfaces of thin film give rise to interference effects of the substrate coatings and the variable optical properties of prior level semiconductor substrate structures, and it can be contributed to substantial errors in detecting and determining the actual "top surface" of semiconductor substrates [2] .…”

Section: Introductionmentioning

confidence: 99%

The Application of AGILE for 40nm Via Hole Development of Lithography Process and Solutions

et al. 2014

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As the chip industry enters 45/40 nm technology node and beyond, Via photolithography process is becoming more and more challenging due to decrease of critical dimension (CD) and narrow process window. The effective control on Via CDU becomes more important to improve SRAM yield, however, the CDU has shown highly sensitive to the variations of wafer topography and the leveling capability of a scanner. The Air Gauge Improved Process Leveling (AGILE) function of ASML immersion scanner is a very effective leveling system for the improvement of CDU performance. This paper studies on the implementation and performance of AGILE focus corrections for advanced photo lithography in volume production as well as advanced development in Huali’s 300 mm facility. In particular, a logic hierarchy that manages the air gage sub-system corrections to optimize tool productivity with sufficient sampling frequency to ensure focus accuracy for stable production processes is described.

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Section: Introductionmentioning

confidence: 99%

The Application of AGILE for 40nm Via Hole Development of Lithography Process and Solutions

et al. 2014

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Monitoring process-induced focus errors using high-resolution flatness metrology

Morgenfeld

Brunner

Nummy

et al. 2015

2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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Reducing focus errors during optical lithography patterning is crucial for minimizing defects and for achieving the desired critical dimension uniformity (CDU). Factors that contribute to lithography defocus originate from both within and outside the exposure tools. Wafer geometry and topography have been shown to be a major contributor to the focus budget, but decoupling wafer issues from scanner tooling / chuck signatures is far from trivial. In this paper we will review how the use of flatness metrology in a 22nm manufacturing environment improved our ability to measure focus errors as well as enabled the decoupling of error between tooling and wafer sources. We will also review several examples of experimental datasets demonstrating how this wafer shape measurement technique has provided unique insight to the nature of topography based focus error, as well as provide a valuable learning mechanism for driving improvement in process cycles of learning.

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Application of automated topography focus corrections for volume manufacturing

Cited by 2 publications

References 0 publications

The Application of AGILE for 40nm Via Hole Development of Lithography Process and Solutions

The Application of AGILE for 40nm Via Hole Development of Lithography Process and Solutions

Monitoring process-induced focus errors using high-resolution flatness metrology

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