Approximate Arithmetic Circuits: Design and Evaluation

Jiang, Honglan; Liu, Leibo; Lombardi, Fabrizio; Han, Jie

doi:10.1007/978-3-319-99322-5_4

Cited by 18 publications

(8 citation statements)

References 23 publications

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“…The minimum delay occurs in many cases when no carry is involved [27]. The random delay is expressed by Log2 N, where N is the number of bits of RCA [28].…”

Section: B Completion Detectormentioning

confidence: 99%

An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline

Ghafoor¹,

Mughal

Khan

2021

IEEE Access

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Asynchronous systems are native to a full custom domain. Their implementation using auto place-and-route tools requires dynamic calibration of interconnects delays in addition to the placement of predefined static delay elements. This paper presents a completion detector for a single-rail bit encoded datapath that, as an adaptive-delay element, eliminates the need to insert any predefined delay element and caters to routing delays dynamically. A programmable pulse-generator is also proposed that empowers the designers to generate clock signals based on the timing report obtained from the CAD tool to drive various synchronous subsystems and embedded resources like BRAMs in FPGAs. Employing these components, we present an asynchronous pipeline model with implicit control to expedite migration from the traditional synchronous pipelines to their asynchronous counterparts. A single-rail bit encoded datapath has been used to utilize chip area effectively instead of a delay-insensitive dual-rail datapath, and a two-phase handshake protocol has been adopted as opposed to a four-phase handshake protocol to lower handshaking overhead. A RISC processor validates the proposed asynchronous pipeline model, exhibiting a smooth functionality and power-delay parameter comparable to that of a synchronous pipeline, in addition to ease of routing and avoiding clock skews in a complex system-on-chip.

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“…The minimum delay occurs in many cases when no carry is involved [27]. The random delay is expressed by Log2 N, where N is the number of bits of RCA [28].…”

Section: B Completion Detectormentioning

confidence: 99%

An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline

Ghafoor¹,

Mughal

Khan

2021

IEEE Access

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“…The original circuits of EvoApprox8b are red points, conventional broken array multipliers are green points, and truncated multipliers are blue points. Purple color denotes other multipliers analyzed in [56] (approximate multipliers (AM), error-tolerant multipliers (ETM), and underdesigned multipliers (UDM)) and lpAClib multipliers [57]. The grey points in Fig.…”

Section: A Gate Level Approximationsmentioning

confidence: 99%

“…Each approximate circuit is fully characterized in terms of Fig. 1: The MAE-power plot for 8-bit approximate multipliers taken from the EvoApproxLib-LITE (black points), EvoApproxLib (grey points), and EvoApprox8b (red points) are compared with broken array multipliers (green points), truncated multipliers (blue points) and other selected approximate multipliers from lpAClib [57] and [56]. Adopted from [55].…”

Section: A Gate Level Approximationsmentioning

confidence: 99%

Evolutionary Algorithms in Approximate Computing: A Survey

Sekanina

2021

JICS

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In recent years, many design automation methods have been developed to routinely create approximate implementations of circuits and programs that show excellent trade-offs between the quality of output and required resources. This paper deals with evolutionary approximation as one of the popular approximation methods. The paper provides the first survey of evolutionary algorithm (EA)-based approaches applied in the context of approximate computing. The survey reveals that EAs are primarily applied as multi-objective optimizers. We propose to divide these approaches into two main classes: (i) parameter optimization in which the EA optimizes a vector of system parameters, and (ii) synthesis and optimization in which EA is responsible for determining the architecture and parameters of the resulting system. The evolutionary approximation has been applied at all levels of design abstraction and in many different applications. The neural architecture search enabling the automated hardware-aware design of approximate deep neural networks was identified as a newly emerging topic in this area.

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“…Alternatively, custom training loops that implement quantization-aware weights learning [35][36][37] represent a faster and more reliable option than fine-tuning. At the hardware level, several custom designs make use of lightweight inexact MAC units integrated into the data-path [15,[38][39][40] to accelerate the arithmetic workload.…”

Section: Convnets Approximation Via Arithmetic Approximation and Data-reusementioning

confidence: 99%

AxP: A HW-SW Co-Design Pipeline for Energy-Efficient Approximated ConvNets via Associative Matching

Mocerino

Calimera

2021

Applied Sciences

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The reduction in energy consumption is key for deep neural networks (DNNs) to ensure usability and reliability, whether they are deployed on low-power end-nodes with limited resources or high-performance platforms that serve large pools of users. Leveraging the over-parametrization shown by many DNN models, convolutional neural networks (ConvNets) in particular, energy efficiency can be improved substantially preserving the model accuracy. The solution proposed in this work exploits the intrinsic redundancy of ConvNets to maximize the reuse of partial arithmetic results during the inference stages. Specifically, the weight-set of a given ConvNet is discretized through a clustering procedure such that the largest possible number of inner multiplications fall into predefined bins; this allows an off-line computation of the most frequent results, which in turn can be stored locally and retrieved when needed during the forward pass. Such a reuse mechanism leads to remarkable energy savings with the aid of a custom processing element (PE) that integrates an associative memory with a standard floating-point unit (FPU). Moreover, the adoption of an approximate associative rule based on a partial bit-match increases the hit rate over the pre-computed results, maximizing the energy reduction even further. Results collected on a set of ConvNets trained for computer vision and speech processing tasks reveal that the proposed associative-based hw-sw co-design achieves up to 77% in energy savings with less than 1% in accuracy loss.

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Approximate Arithmetic Circuits: Design and Evaluation

Cited by 18 publications

References 23 publications

An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline

An FPGA Compliant Single-Rail Encoded Asynchronous Pipeline

Evolutionary Algorithms in Approximate Computing: A Survey

AxP: A HW-SW Co-Design Pipeline for Energy-Efficient Approximated ConvNets via Associative Matching

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