Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path From Specification to Prototyp 2016
DOI: 10.1145/2990299.2990306
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Architectural performance analysis of FPGA synthesized LEON processors

Abstract: Current processors have gone through multiple internal optimization to speed-up the average execution time e.g. pipelines, branch prediction. Besides, internal communication mechanisms and shared resources like caches or buses have a significant impact on Worst-Case Execution Times (WCETs). Having an accurate estimate of a WCET is now a challenge. Probabilistic approaches provide a viable alternative to single WCET estimation. They consider WCET as a probabilistic distribution associated to uncertainty or risk… Show more

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Cited by 3 publications
(2 citation statements)
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“…Before each run, inputs of the components are shuffled or randomly generated. Then, caches are flushed as explained in [64] and current time is fetched from RTOS which basically gets the current time value from a timer in nanoseconds resolution.…”
Section: Definition Of Inputsmentioning
confidence: 99%
“…Before each run, inputs of the components are shuffled or randomly generated. Then, caches are flushed as explained in [64] and current time is fetched from RTOS which basically gets the current time value from a timer in nanoseconds resolution.…”
Section: Definition Of Inputsmentioning
confidence: 99%
“…Some effort has been dedicated in previous works to identify the best model that fits the worst-case execution time values. The results are controversial: some researchers [2,10,11,25] claim we should consider only the Weibull or Gumbel distribution, while others [30,44] do not exclude the Fréchet too. The Gumbel distribution is often the only one taken into account because it is an upper-bound of the Weibull, however, it is not always possible to use such upper-bound strategy without hindering the result reliability [38].…”
Section: Evt Distribution Classesmentioning
confidence: 99%