Architecture and C++-programming environment of a highly parallel image signal processor

Kneip, J.; Ohmacht, Martin; Ronner, K.; Pirsch, P.

doi:10.1016/0165-6074(95)00023-h

Cited by 8 publications

(1 citation statement)

References 17 publications

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“…By combining instruction word level parallelism (VLIW), data parallelism (multiple data paths, split ALU capability) and transfer parallelism (autonomous DMA unit), a high degree of concurrent processing can be achieved for various algorithms [1] [2]. The SIMD controlling principle leads to low hardware implementation cost compared with MIMD or multithreaded approaches.…”

Section: Architecturementioning

confidence: 99%

Realization of a programmable parallel DSP for high performance image processing applications

Wittenburg

Berekovic²,

Hinrichs³

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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Architecture and design of the HiPAR-DSP, a SIMD controlled signal processor with parallel data paths, VLIW and novel memory design. The processor architecture is derived from an analysis of the target algorithms and specified in VHDL on register transfer level. A team of more than 20 graduate students covered the whole design process, including the synthesizable VHDL description, synthesis, routing and backannotation as the development of a complete software development environment. The 175mm 2 , 0.5m 3LM CMOS design with 1.2 million transistors operates at 80 MHz and achieves a sustained performance of more than 600 million arithmetic operations.

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Section: Architecturementioning

confidence: 99%