Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads

performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.

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VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

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Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads

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References 26 publications

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

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