Architectures for Analog Motion Estimation Processors: A Comparison

Panovic, M.; Demosthenous, Andreas

doi:10.1109/iscas.2005.1465648

Cited by 2 publications

(1 citation statement)

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“…For the CNN-based image stabilization architecture presented in [4] no power consumption or processing figures were given. Additionally, the effect of error in the ME distortion measure has been studied in [20,21].…”

Section: Related Workmentioning

confidence: 99%

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

Poikonen

Laiho

Paasio

et al. 2009

EURASIP J. Adv. Signal Process.

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A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations , reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 μm CMOS technology.

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Section: Related Workmentioning

confidence: 99%