Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding

Abstract

High Efficiency Video Coding (HEVC) is the newest video coding standard beyond H.264/AVC. To more efficiently compress image frames, variable block size DCT/IDCT (from 4 × 4 to 32 × 32) as well as 4 × 4 DST/IDST is employed by HEVC. In this paper, a novel area-efficient IDCT/IDST architecture for Ultra-High Definition (UHD) video applications is proposed. To reduce hardware cost and improve throughput efficiency, a novel resource sharing scheme, a template-based constant multiplication structure and a transpose buffer structure are adopted. Experimental results show that the proposed architecture can address 8K × 4K (7680 × 4320, 30 fps) video sequences at 390 MHz with at least a 39.5% gate count savings. Consequently, the proposed architecture offers a cost-efficient solution for future UHD applications.

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

“…According to the findings presented in Table 4, the 2D-IDCT/IDST architecture proposed in this paper yields an area optimization of about 39% and 16% with less performance compared to [5] and [6], respectively,…”

“…However, our proposed designs for 2D-IDCT/IDST and IQ/IT can reach 1080 p at 30 fps and 1080 p at 25 fps in worst case, respectively. Hence, our designs have better performances than [4] and [7] in terms of frame rate and use lower gate count than [5] and [6]. Table 5 presents the complete synthesis results of the 2D-IDCT/IDST and the IQ/IT architectures under the Zynq XC7Z020 FPGA and the comparison with related works.…”

“…Chiang el al. [5] Liang et al [6] Goebel et al [ On the other hand, the designs [4] and [7] propose the implementation only of the 1D-DCT which can achieve 1080 p at 67 fps and 1080 p at 30 fps, respectively. However, our proposed designs for 2D-IDCT/IDST and IQ/IT can reach 1080 p at 30 fps and 1080 p at 25 fps in worst case, respectively.…”

“…This architecture has since not only reduced the occupied area significantly and also met the throughput of 3840 × 2160 at 30 fps using CMOS 90 nm technology. However, Liang et al [6] present an architecture that supports the 2D integer inverse discrete sine transform (2D-IDST) and 2D integer inverse discrete cosine transform (2D-IDCT) using two 1D-IDCT/IDST units and memory block. This architecture calculates 4 residual pixels in parallel in each clock cycle.…”

A new area and power efficient DCT circuits using sporadic logarithmic shifters

“…HEVC [8] was finalized in 2013 and is set to replace H.264/AVC [9]. With the growing subscription of mobile multimedia services which involve the H.265/ HEVC standards [10], it becomes imperative to improve the hardware implementation such that it can consume less power which is essential particularly for mobile devices. One of the essential cores of these video codecs is Discrete Cosine Transform (DCT).…”