Area Efficient Rapid Signal Acquisition scheme for High Doppler DSSS Signals

Abstract

The Direct Sequence Spread Spectrum (DSSS) communication system is widely used in ground to air missile links due to its anti-jam and low Signal to Noise Ratio (SNR) requirement advantages. The paper presents the challenges in achieving fast signal acquisition in this scenario and brings out the implementation challenges for achieving simultaneous Doppler estimation and phase delay of Pseudo Noise (PN) code. A new scheme for PN code phase delay estimation with correlation of differential signals, followed by precise Doppler estimation using Fast Fourier Transform (FFT) is presented. The area optimized Field Programmable Gate Array (FPGA) friendly architecture is utilized for rapid signal acquisition by combining both time and frequency domain approaches. The advanced design practices inFPGAs are used to achieve resource sharing and high clock speed of operation. The architecture is synthesized for Virtex-6 LX240T FPGA, resulting in 52% of area occupancy and 134 MHz of maximum allowed clock frequency value.