Area-I/O flip-chip routing for chip-package co-design

Fang, Jia-Wei; Chang, Yao-Wen

doi:10.1109/iccad.2008.4681624

Cited by 8 publications

References 6 publications

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Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Yin,

Jin,

Chen

et al. 2023

IEEE Access

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In recent years, there has been extensive research on the routing problem of printed circuit boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical constraints, manual PCB routing has become a time-consuming task to achieve design convergence. Previous work decomposed the problem into escape routing and area routing, focusing on these problems separately. However, there was always a gap between these two problems, requiring significant human effort for iterative algorithm adjustments. Furthermore, previous area routing work mainly focused on routing between ball grid array (BGA) packages in escape routing. However, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. Therefore, it is necessary to study a unified routing approach. The current unified routing approach adopts the A* algorithm, but there is still room for improvement in routing speed. This paper proposes a new algorithm called Unet-Astar, which accelerates the routing efficiency by employing deep learning algorithms in a simulated environment. Additionally, a Deeper Unet is proposed for generating recommended regions for the routing algorithm. The new network structure can provide more contextual information, thereby improving routing efficiency. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm. Specifically, for all given test cases, our router achieves approximately a 70% improvement in runtime speed compared to the old router. Another major contribution of this work is the development of a routing problem set generator, which can generate parameterized routing problem sets with different sizes and constraints. This enables the evaluation of different routing algorithms and the generation of training datasets for future data-driven routing methods. All the code has been open-sourced and can be found at https://github.com/Firesuiry/Unet-Astar-For-PCB-Routing. INDEX TERMS physical design, printed circuit board, routing, Machine learning I. INTRODUCTION 1 This article has been accepted for publication in IEEE Access.

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Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Yin,

Jin,

Chen

et al. 2023

IEEE Access

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Routability-driven partitioning-based IO assignment for flip-chip designs

Yan

Chen

2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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Given a set of n IO buffers and a set of n bump balls on a re-distribution routing layer, an O(n(logn) 2 ) routabilitydriven partition-based IO assignment is proposed to assign n IO connections for RDL routing in a flip-chip design. Firstly, based on the recursive partition of bump balls and IO buffers, the partition-based IO assignment can be obtained by using the geometrical mapping between bump balls and IO buffers. Furthermore, according to the routability definition of all the IO connections, the unroutable IO connections are reassigned. The experimental results show that our proposed partitionbased IO assignment can maintain 100% routability for RDL routing in tested circuits. Compared with the Delaunarytriangulation-based IO assignment[4] in total wirelength and CPU time, our partition-based IO assignment only increases the total wirelength by 0.17% and saves the CPU time by 23.8% on the average.

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