Area-oriented synthesis for pass-transistor logic

Chaudhry, Rochika G.; Liu, T.-H.; Aziz, Adnan; Burns, J.L.

doi:10.1109/iccd.1998.727037

Cited by 24 publications

(22 citation statements)

References 13 publications

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“…Table 3 compares our result with the results reported in [2], [3] and [4]. The number of nodes according to [2], delay-oriented synthesis presented in [3], area-delay oriented synthesis presented in [4] and based on RP-based heuristic of the present work are presented in Columns 2, 3, 4 and 5 of the Table 3, respectively. It is observed that the experimental results based on our approach are superior with respect to the existing reported results.…”

Section: Implementation and Experimental Resultsmentioning

confidence: 50%

“…In [2], [3] and [4] results were reported in terms of the number of nodes in synthesized circuits. Table 3 compares our result with the results reported in [2], [3] and [4].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

“…As the size of BDDs is more important than the same ordering of variables through different paths, we have adopted this new approach. Efficacy of this heuristic has been established by comparing the sizes of BDDs obtained using our approach with those works reported in [2], [3] and [4].…”

Section: Introductionmentioning

confidence: 99%

“…These smaller BDDs can be optimized with ease and the approach allows synthesis of any arbitrary function with large number of variables. Liu et al [3] and Chaudhury et al [4] have proposed performance-oriented and areaoriented optimization techniques based on the decomposed BDDs.…”

Section: Introductionmentioning

confidence: 99%

“…As a consequence, in the present era of sub-micron technology, driven by the need for low power and high performance, researchers are looking for better alternatives. Recent studies [1]- [4] show that pass transistor logic (PTL) circuits provide superior performance in terms of area, delay and power. However, PTL circuits have some inherent limitations, such as threshold voltage drop across pass transistors, possibility of sneak paths and higher delay for cascaded pass transistors.…”

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confidence: 99%

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Synthesis of high performance low power PTL circuits

Samanta

Dharmadeep

Pal

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Abstract-Among the various CMOS logic families, PTL has been recognized as one of the potential alternatives to static CMOS for the synthesis of high performance and low power circuits. Moreover, as BDDs can be readily mapped to PTL circuits, use of BDDs has been synonymous with the synthesis of PTL circuits. Most of the reported works on PTL synthesis are based on the Reduced Ordered BDDs (ROBDDs). We have developed a novel heuristic-based technique for obtaining Reduced Unordered BDDs (RUBDDs), which leads to circuits of smaller size having lesser delay and smaller power consumption compared to the existing results. We propose the technology mapping using the popular LEAP-like cells, such that the PTL circuit synthesis flow has the same flavor as that of the standard cell-based static CMOS circuit synthesis. We have also developed models for the estimation of delay and power consumption of the synthesized PTL circuits and compared those with the static CMOS and other existing PTL-based circuit realizations. I IntroductionIn recent years, static CMOS has emerged as the technology of choice for VLSI circuit realization, because of the ease of design, robustness, scalability and other advantages that this logic style offers. But, static CMOS uses both pMOS and nMOS transistor networks, taking larger area, incurring more delay and higher power dissipation. As a consequence, in the present era of sub-micron technology, driven by the need for low power and high performance, researchers are looking for better alternatives. Recent studies [1]- [4] show that pass transistor logic (PTL) circuits provide superior performance in terms of area, delay and power. However, PTL circuits have some inherent limitations, such as threshold voltage drop across pass transistors, possibility of sneak paths and higher delay for cascaded pass transistors. While synthesizing PTL circuits, care should be taken to overcome these limitations.Although PTL is a promising alternative to static CMOS, it demands for a radically different logic synthesis approach. It has been observed that binary decision diagram (BDD) representation of a logic function can be readily mapped onto a PTL network. Moreover, BDD-based synthesis avoids some of the limitations mentioned above. This has made BDD-based approach very attractive for the synthesis of PTL circuits. In earlier works In this paper, we have also used decomposed BDDs for PTL circuits synthesis. In addition to using decomposed BDDs, we have used a new heuristic, based on ratio parameters (RP), for optimal variable ordering. The concept of RP was used earlier [6], [7] for the synthesis of multiplexer-based circuits. The RP-based heuristic helps in obtaining BDDs with smaller number of nodes. However, BDDs generated by this approach may not have the same ordering of variables at the same level along different paths. These BDDs may be termed as Reduced Unordered BDDs (RUBDDs), in contrast to Reduced Ordered BDDs (ROBDDs) commonly used in the existing approaches. As the size of BDDs is more importan...

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Section: Implementation and Experimental Resultsmentioning

confidence: 50%

“…In [2], [3] and [4] results were reported in terms of the number of nodes in synthesized circuits. Table 3 compares our result with the results reported in [2], [3] and [4].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Synthesis of high performance low power PTL circuits

Samanta

Dharmadeep

Pal

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

Günther¹,

Drechsler²

2000

Journal of Systems Architecture

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Synthesis of high performance low power PTL circuits

Samanta¹,

Dharmadeep²,

Pal³

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

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Among the various CMOS logic families, PTL has been recognized as one of the potential alternatives to static CMOS for the synthesis of high performance and low power circuits. Moreover, as BDDs can be readily mapped to PTL circuits, use of BDDs has been synonymous with the synthesis of PTL circuits. Most of the reported works on PTL synthesis are based on the Reduced Ordered BDDs (ROBDDs). We have developed a novel heuristic-based technique for obtaining Reduced Unordered BDDs (RUBDDs), which leads to circuits of smaller size having lesser delay and smaller power consumption compared to the existing results. We propose the technology mapping using the popular LEAP-like cells, such that the PTL circuit synthesis flow has the same flavor as that of the standard cell-based static CMOS circuit synthesis. We have also developed models for the estimation of delay and power consumption of the synthesized PTL circuits and compared those with the static CMOS and other existing PTL-based circuit realizations. I Introduction In recent years, static CMOS has emerged as the technology of choice for VLSI circuit realization, because of the ease of design, robustness, scalability and other advantages that this logic style offers. But, static CMOS uses both pMOS and nMOS transistor networks, taking larger area, incurring more delay and higher power dissipation. As a consequence, in the present era of sub-micron technology, driven by the need for low power and high performance, researchers are looking for better alternatives. Recent studies [1]-[4] show that pass transistor logic (PTL) circuits provide superior performance in terms of area, delay and power. However, PTL circuits have some inherent limitations, such as threshold voltage drop across pass transistors, possibility of sneak paths and higher delay for cascaded pass transistors. While synthesizing PTL circuits, care should be taken to overcome these limitations. Although PTL is a promising alternative to static CMOS, it demands for a radically different logic synthesis approach. It has been observed that binary decision diagram (BDD) representation of a logic function can be readily mapped onto a PTL network. Moreover, BDD-based synthesis avoids some of the limitations mentioned above. This has made BDD-based approach very attractive for the synthesis of PTL circuits. In earlier works [1] and [5], BDDs of the complete functions called monolithic BDDs, were constructed before technology mapping on PTL cells. The size of the monolithic BDDs grow exponentially with the number of input variables of the functions, making the approach unsuitable for functions of large number of variables, which is common in present-day VLSI circuits. Decomposed-BDD approach [2] has been proposed to overcome this problem. In decomposed-BDD approach, instead of creating a single big monolithic BDD, compact BDDs in terms of intermediate variables are constructed. These smaller BDDs can be optimized with ease and the approach allows synthesis of any arbitrary function with large number of varia...

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Area-oriented synthesis for pass-transistor logic

Cited by 24 publications

References 13 publications

Synthesis of high performance low power PTL circuits

Synthesis of high performance low power PTL circuits

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

Synthesis of high performance low power PTL circuits

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