Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers

et al. 2016

IEEE Trans. VLSI Syst.

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In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result in a design in which data are transferred in a pipelined fashion, from the local memory of the sending core to the local memory of the receiving core, without any dynamic arbitration, buffering, and clock synchronization. The routers use two-phase bundled-data handshake latches based on the Mousetrap latch controller and are extended with a clock gating mechanism to reduce the energy consumption. The NIs integrate the direct memory access functionality and the TDM schedule, and use dual-ported local memories to avoid buffering, flow-control, and synchronization. To verify the design, we have implemented a 4 × 4 bitorus NoC in 65-nm CMOS technology and we present results on area, speed, and energy consumption for the router, NI, NoC, and postlayout.

“…The details of the analysis can be found in [19]. The results show that a 2 × 2 instance of Argo can tolerate up to three clock cycles of skew, depending on the operating frequency.…”

Section: Timing Organizationmentioning

confidence: 94%

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

Kasapaki

Schoeberl

et al. 2016

IEEE Trans. VLSI Syst.

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“…First, the DMA controllers are moved into the network interfaces and tightly integrated with the TDM scheduling [18], as illustrated in Figure 1. Second, the Argo NoC use asynchronous routers [5], [19]. The result is a hardware-efficient implementation that at the same time enables a globally asynchronous, locally synchronous timing organization of the entire multiprocessor platform.…”

Section: The T-crest Multicore Processormentioning

confidence: 99%

Avionics Applications on a Time-Predictable Chip-Multiprocessor

Rocha

Silva

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

et al. 2016

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Avionics applications need to be certified for the highest criticality standard. This certification includes schedulability analysis and worst-case execution time (WCET) analysis. WCET analysis is only possible when the software is written to be WCET analyzable and when the platform is time-predictable. In this paper we present prototype avionics applications that have been ported to the time-predictable T-CREST platform. The applications are WCET analyzable, and T-CREST is supported by the aiT WCET analyzer. This combination allows us to provide WCET bounds of avionic tasks, even when executing on a multicore processor.

“…Early examples of TDM based NoC's are Nostrum [31] and AEtheral/aelite [32] that is used in the CompSoC multiprocessor platform [33]. More recently we have developed the Argo NoC [34], [35], [36], [37]. Argo has a very efficient implementation due to the use of asynchronous routers and a novel NI architecture.…”

Section: Network-on-chipmentioning

confidence: 99%

Models of Communication for Multicore Processors

Schoeberl

2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops

Sparsø

2015

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Abstract-To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.g., shared caches with cache coherency protocols, core-tocore networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability of the different models of communication for realtime systems.