Arithmetic on the European logarithmic microprocessor

Coleman, J.N.; Chester, Ed; Softley, C.I.; Kadlec, J.

doi:10.1109/12.863040

Cited by 116 publications

(107 citation statements)

References 14 publications

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“…LNS representation equivalent to the 32-bit (single precision) IEEE standard FP format [13] has a 31-bit logarithm part that forms a 2's-complement fixedpoint value ranging from -128 to approximately +128. The real numbers represented are signed and have magnitudes ranging from 2 -128 to ~2 +128 (i.e., from 2.9  10 -39 to 3.4  10 +38 ).…”

Section: Background and Terminologymentioning

confidence: 99%

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Logarithmic arithmetic as an alternative to floating-point: A review

Chugh

Parhami

2013

2013 Asilomar Conference on Signals, Systems and Computers

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Section: Background and Terminologymentioning

confidence: 99%

“…At about the same time, a European project, initiated by Coleman et al [13], [14], laid down the foundations for the development of such a commercial digital system, dubbed the European logarithmic microprocessor (ELM), which provided performance similar to commercial superscalar pipelined floating-point processors [15].…”

Section: Introductionmentioning

confidence: 99%

Logarithmic arithmetic as an alternative to floating-point: A review

Chugh

Parhami

2013

2013 Asilomar Conference on Signals, Systems and Computers

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“…In contrast, the novel representation proposed here may accomplish similar gradual underflow using simple algorithms that do not explicitly refer to the magnitude of the operands or results. The simple algorithms proposed here will be much more efficient than those of [2] in a software-based gradualunderflow implementation (for instance, on the the ELM [9], [17], a microprocessor that provides hardware for SLNSwithout-denormals). Furthermore, while [2] only applies to denormals patterned after IEEE-754, the novel approach in this paper suggests a range of denormal representations (from one similar to IEEE-754 to a fully-denormal one similar to the µ-law for speech encoding [30]).…”

Section: Introductionmentioning

confidence: 99%

“…Successful applications have included massive scientific simulation [24], Hidden-Markov Models (HMM) [28], and music synthesis [20]. The European Logarithmic Microprocessor (ELM) [9] provides dual SLNS ALUs that implement the Gauss/Leonelli algorithm in 0.18 µm 125MHz hardware. More recently, advances in FPGA [13] and cotransformation [17] implementations of SLNS allow higher-precision applications to be affordable.…”

Section: Introductionmentioning

confidence: 99%

The Denormal Logarithmic Number System

Arnold¹,

Collange

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-Economical hardware often uses a FiXed-point Number System (FXNS), whose constant absolute precision is acceptable for many signal-processing algorithms. The almostconstant relative precision of the more expensive Floating-Point (FP) number system simplifies design, for example, by eliminating worries about FXNS overflow because the range of FP is much larger than FXNS for the same wordsize; however, primitive FP introduces another problem: underflow. The conventional Signed Logarithmic Number System (SLNS) offers similar range and precision as FP with much better performance (in terms of power, speed and area) for multiplication, division, powers and roots. Moderate-precision addition in SLNS uses table lookup with properties similar to FP (including underflow). This paper proposes a new number system, called the Denormal LNS (DLNS), which is a hybrid of the properties of FXNS and SLNS. The inspiration for DLNS comes from the denormal numbers found in IEEE-754 (that provide better, gradual underflow) and the µ-law often used for speech encoding; the novel DLNS circuit here allows arithmetic to be performed directly on such encoded data. The proposed approach allows customizing the range in which gradual underflow occurs. A wide gradual underflow range acts like FXNS; a narrow one acts like SLNS. Simulation of an FFT application illustrates a moderate gradual underflow decreasing bit-switching activity 15% compared to underflowfree SLNS, at the cost of increasing application error by 30%. DLNS reduces switching activity 5% to 20% more than an abruptly-underflowing SLNS with one-half the error. Synthesis shows the novel circuit primarily consists of traditional SLNS addition and subtraction tables, with additional datapaths that allow the novel ALU to act on conventional SLNS as well as DLNS and mixed data, for a worst-case area overhead of 26%.

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“…Hence the computations are based on logarithmic floating point computations rather than conventional floating point arithmetic units. [14]. several algorithms have been developed for coding wavelet coefficients.…”

Section: Introductionmentioning

confidence: 99%