ARMing the Next Generation of Spaceflight Embedded Platforms Through Processor Reusability

Henderson, Kayla; Wiatrek, Nathan; Saenz, Patrick

doi:10.1109/aero55745.2023.10115627

Cited by 1 publication

(1 citation statement)

References 3 publications

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“…ESA also provides NIR HAWAII-2RG BM algorithm to benchmark on-board payload processing on multi-core processors [32]. Moreover, micro-benchmarks exist to compare performance and power characteristics of Arm Cortex-72 cores with current space-rated processors [33], such as Dhyrstones, Whetstones, and CoreMark. To the best of our knowledge, open-source embedded C/C++ benchmarks conforming with the above constraints and dedicated to the surveyed space algorithms, are not available.…”

Section: Benchmark For Hw/sw Designmentioning

confidence: 99%

On-board Payload Data Processing Combined with the Roofline Model for Hardware/Software Design

Lee,

Casseau,

Kritikakou

et al. 2024

2024 IEEE Aerospace Conference

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High-performance on-board payload data processing has become more interesting with the development of radiationhardened multiprocessor System-on-chip (MPSoC). As recent space-qualified MPSoCs include Arm Central Processing Units (CPUs) and Field Programmable Gate Arrays (FPGAs), an efficient design method is required to deal with complex heterogeneous embedded systems. Both data bit-width (data accuracy) and processing performance are important in astronomy, thus the design methodology should concern application-specific Multi-Objective Optimization Problems (MOOPs). This paper proposes to combine the roofline performance model with Design Space Exploration (DSE) of hardware/software designs as a methodology. We use High-Level Synthesis (HLS) for FPGA design to configure different hardware architectures based on C/C++ and pragmas. We develop a benchmark for payload data processing on Arm CPUs and embedded FPGA on a heterogeneous MPSoC by adapting open-source libraries for one of the most commonly used algorithms to provide validated libraries to payload teams. The benchmark takes as constraints the SVOM ECLAIRs payload requirements, and as input data the CCSDS test images, executes applications, and verifies output data. We chose an AMD-Xilinx Zynq UltraScale+ evaluation board and the two-Dimensional Fast Fourier Transform (2-D FFT) as a DSE use case. We designed the benchmark on an Arm Cortex-A53 in bare-metal and an embedded FPGA based on Vitis HLS. The results show a customized roofline model with the hardware/software design. The implemented design has 1.6-55 times faster performance compared to the payload execution time requirement. Based on the proposed roofline model and the DSE results, future payload teams can study the trade-off between execution time and area efficiency to select the most suitable implementation.

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Section: Benchmark For Hw/sw Designmentioning

confidence: 99%