2018 IEEE 36th International Conference on Computer Design (ICCD) 2018
DOI: 10.1109/iccd.2018.00028
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Array Tracking Prefetcher for Indirect Accesses

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Cited by 2 publications
(10 citation statements)
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“…The four NT variants: prefetcher-only (ntpf), prefetcher with BOS (ntpf+bos), pre-execution unit (ntpx), and pre-execution unit with BOS (ntpx+bos) evaluated in this article achieve 4.1×, 11.9×, 14.9×, and 18.8× speedups, respectively, on average, over a no-prefetching baseline. In contrast, AMAC [1] and ATP [11] provided 2.4× and 1.2× speedups, respectively. Other recent prefetchers (BO [16], ISB [18], and SPP [17]) do not offer significant performance gains for the workloads in this article.…”
Section: Introductionmentioning
confidence: 90%
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“…The four NT variants: prefetcher-only (ntpf), prefetcher with BOS (ntpf+bos), pre-execution unit (ntpx), and pre-execution unit with BOS (ntpx+bos) evaluated in this article achieve 4.1×, 11.9×, 14.9×, and 18.8× speedups, respectively, on average, over a no-prefetching baseline. In contrast, AMAC [1] and ATP [11] provided 2.4× and 1.2× speedups, respectively. Other recent prefetchers (BO [16], ISB [18], and SPP [17]) do not offer significant performance gains for the workloads in this article.…”
Section: Introductionmentioning
confidence: 90%
“…This allows multiple LDS traversal-misses from different lookups to overlap, increasing MLP. Similarly to recent prefetchers [3,11] and on-chip accelerators [4,12], NT reduces design cost and complexity through tight integration with the core, eliminating the need for dedicated TLB and cache units.…”
Section: Nt Architecture Overviewmentioning
confidence: 99%
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