ASA-FTL: An adaptive separation aware flash translation layer for solid state drives

Xie, Wei; Chen, Yong; Roth, Philip C.

doi:10.1016/j.parco.2016.10.006

Cited by 14 publications

(4 citation statements)

References 22 publications

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“…In ASA-FTL: An Adaptive Separation Flash Translation layer for SSDs data is divided into three groups; Hot, Cold and Warm [29]. In fact, the space of the memory blocks is divided, so that each data is stored into one of three groups according to its characteristics.…”

Section: B the Previous Designated Ftlsmentioning

confidence: 99%

Improving Utilization and Life-Span in Parallel Aware MLC-Based SSD Using Virtual Blocks

Forouhar

Safaei

2020

IEEE Access

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FTL (Flash Translation Layer) is a memory block controller that manages the challenges of a data storage system based on flash memory technology. The design of internal parallelism in MLC-based SSDs with virtual blocks resulted in various challenges and due to the physical structure of flash memory cells based on MLC technology, it is possible to write a new page in a data block at the address after the last page is written. In parallel-based SSD design based on virtual blocks, some writes create unusable pages at the memory space, and these created holes reduce memory efficiency; consequently, it reduces the life-time of memory blocks by creating more operations, and accelerates garbage collection and merging operations. The proposed FTL offers three steps to address this constraint. Firstly, an idea was proposed to prevent costly transitions and to distribute data more evenly at memory blocks (wear leveling). Secondly, the unused holes created in virtual blocks became much fewer resulting in increased utilization of memory space. At last, a policy was proposed to prevent update blocks (log blocks) from being blocked and to postpone the merging and garbage collection by which the memory lifetime increases significantly. Simulation results showed that the number of unused erased pages and the number of extra write operations decreased up to 23% and 17%, respectively. In addition, the number of invalid released pages increased up to 21% in the proposed FTL, and the speed of I/O executions to 3%.INDEX TERMS Solid-state disk, MLC (multi-level cell), parallel virtual blocks, flash translation layer, life-span, memory utilization.

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Section: B the Previous Designated Ftlsmentioning

confidence: 99%

Improving Utilization and Life-Span in Parallel Aware MLC-Based SSD Using Virtual Blocks

Forouhar

Safaei

2020

IEEE Access

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“…If the upper level criterion is extremely low, then the SLC blocks become significantly worn out, and the garbage collection (GC) overhead of the SLC region is increased, thereby deteriorating storage performance. (2) Because the page copy overhead of GC can be increased when data with different lifespans are stored in the same block [27], storing data of various components to the NAND block together can decrease the performance of the proposed method. In a hybrid SSD, GC occurs frequently in an SLC region composed of a small number of SLC NANDs; therefore, page copying the SLC GC degrades the performance of the proposed method.…”

Section: Introductionmentioning

confidence: 99%

Level Aware Data Placement Technique for Hybrid NAND Flash Storage of Log-Structured Merge-Tree Based Key-Value Store System

et al. 2020

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A log-structured merge-tree-based key value store (LSMKV) is an append-only database for storing and retrieving unstructured data, especially in a write-intensive environment. This database uses hierarchical components to store and manage data. Upper-level components have a shorter data lifespan and a higher access locality than lower-level components. Hence, the data access latency of the upper-level components significantly affects the performance of the entire database. Hybrid solid-state drives (SSD) composed of media with different access speeds can improve the performance of an LSMKV by storing the upper-level components using a fast storage space. However, many hybrid SSDs use fast storage spaces to store data that are frequently allocated to the same logical address; they are not suitable for storing appendonly component data, which are allocated to adjacent logical addresses. This paper proposes a hybrid SSDmanagement method to reduce the data access latency of append-only LSMKVs and increase the durability of hybrid SSDs. The proposed method allocates the data of upper-level components to a fast storage space using the level information of the data as a hint. This study utilizes dynamic data separation to determine the components to be placed in the fast storage space, NAND block management to store the data with similar lifespans in the same fast NAND block, and a data-relocation method to migrate long-lived data from the fast NAND region to another NAND region. Experimental results indicate that the proposed method reduces the average I/O latency by an average of 12% and increases the device durability by an average of 22%.

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“…While the hard disk drive (HDD) no longer meets the growing demand for I/O quality, flash memory excels because of its high performance, light weight, small size, and low energy consumption. Moreover, NAND flash memory has been widely used in Cyber-Physical Systems because technologies such as the multi-level cell, triplelevel cell, and quad-level cell lead to higher bit storage density and thus lower product cost [1]- [4].…”

Section: Introductionmentioning

confidence: 99%

DPW-LRU: An Efficient Buffer Management Policy Based on Dynamic Page Weight for Flash Memory in Cyber-Physical Systems

et al. 2019

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Owing to its high performance, small size, and low energy consumption, NAND flash memory has been extensively adopted in cyber-physical systems. However, the inherent characteristics of flash memory, including not-in-place update and asymmetric I/O latencies, present difficulties in the design of buffer management policies. In this paper, we propose an enhanced buffer management policy for the flash memory referred to as dynamic page weight least recently used (DPW-LRU), which considers temporal locality and simultaneously provides effective utilization of limited buffer resources. Page migration is further enhanced by identifying the page access mode and frequency while separating the buffer into two different regions. A novel eviction algorithm is also designed to reduce the write operations and maintain a high hit ratio of the buffer regions, combining dynamic temporal locality, real-time eviction cost, and recency of pages. The experimental results show that DPW-LRU improves the hit ratio by up to 8.3%, decreases the write operation by up to 22.6%, and reduces the overall latency by up to 18.8% relative to those of other state-of-the-art buffers management policies. INDEX TERMS NAND flash memory, buffer management, flash translation layer, temporal locality.

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ASA-FTL: An adaptive separation aware flash translation layer for solid state drives

Cited by 14 publications

References 22 publications

Improving Utilization and Life-Span in Parallel Aware MLC-Based SSD Using Virtual Blocks

Improving Utilization and Life-Span in Parallel Aware MLC-Based SSD Using Virtual Blocks

Level Aware Data Placement Technique for Hybrid NAND Flash Storage of Log-Structured Merge-Tree Based Key-Value Store System

DPW-LRU: An Efficient Buffer Management Policy Based on Dynamic Page Weight for Flash Memory in Cyber-Physical Systems

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