Aspects of Low-Power High-Speed CMOS VLSI Design: A Review

Ghosh, Prolay; Saha, Tanusree; Kumari, B. Leela

doi:10.1007/978-981-10-3953-9_37

Cited by 3 publications

(2 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For any input over the input terminals A, B, and C, the ALU performs arithmetic and logical operations depending on the input given over the select line. The 8-bit ALU is obtained by cascading all 1-Bit ALU's [18]- [20]. The above block diagram shows the cascaded form of all 1-Bit ALU's.…”

Section: -Bit and 8-bit Alumentioning

confidence: 99%

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

Vijay¹,

Shaik

Shekar³

et al. 2020

International Journal of Systems Applications, Engineering &Amp; Development

View full text Add to dashboard Cite

ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

show abstract

Section: -Bit and 8-bit Alumentioning

confidence: 99%

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

Vijay¹,

Shaik

Shekar³

et al. 2020

International Journal of Systems Applications, Engineering &Amp; Development

View full text Add to dashboard Cite

show abstract

“…As the current portable devices necessitate a huge number of logic gates to assemble in a single integrated chip, the area (or) the size of the chip becomes a major concern. Presently, a single IC incorporates fabrication of around 100,000 or even more transistors in it, thusly calling it VLSI (very large scale integration) [1]. Due to the earlier VLSI technologies relying on speed optimization to improve its performance, it has often suffered from portability issues.…”

Section: Introductionmentioning

confidence: 99%

Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

Dhilipkumar¹,

Mohanbabu²

2022

Intelligent Automation &Amp; Soft Computing

View full text Add to dashboard Cite

Low Power circuits play a significant role in designing large-scale devices with high energy and power consumption. Adiabatic circuits are one such energy-saving circuits that utilize reversible power. Several methodologies used previously infer the use of CMOS circuits for reducing power dissipation in logic circuits. However, CMOS devices hardly manage in maintaining their performance when it comes to fast switching networks. Adiabatic technology is employed to overcome these difficulties, which can further scale down the dissipation of power by charging and discharging. An Efficient Charge Recovery Logic (ECRL) based adiabatic technology is used here to evaluate arithmetic operations in circuits like inverter, full adder, Carry Look-Ahead adder etc. A better chance at reducing delay in digital circuits is illustrated by developing a Kogge-stone Adder, built using the ECRL technology. The developed circuitry is further integrated into a Fast Fourier Transform (FFT), which demonstrates the circuit's enhancement into DSP applications. Not only does this design reduce delay in VLSI switching circuits, but also narrows the power dissipation down to a minimum. This technique proved superior to the existing PFAL technique by demonstrating almost 10% less power dissipation with minimal propagation delay. All the circuits have been simulated at 45 nm technology using the Tanner EDA tool.

show abstract

Design and Implementation of CMOS Full Adder Circuit with ECRL and Sleepy Keeper Technique

Nandal

Kumar

2018

2018 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN)

View full text Add to dashboard Cite

Aspects of Low-Power High-Speed CMOS VLSI Design: A Review

Cited by 3 publications

References 12 publications

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

Design and Implementation of CMOS Full Adder Circuit with ECRL and Sleepy Keeper Technique

Contact Info

Product

Resources

About