Associative memories and processors: An overview and selected bibliography

Parhami, Behrooz

doi:10.1109/proc.1973.9152

Cited by 66 publications

(12 citation statements)

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“…An associative memory [1][2][3][4][5][6][7][8][9][10] can be defined as a memory system with the property that stored data items can be retrieved by their content or part of their content (that is, by the first property of an associative processor). An associative memory has been also called catalog memory [11], contentaddressed memory [12], data-addressed memory [13], parallel search memory [14], search memory [15][16][17], search associative memory [18], content-add~'essable memory [19], distributed logic memory [20], associative pushdown memory [21], and multi-access associative memory [22].…”

Section: Associative Memoriesmentioning

confidence: 99%

“…Because of the rapid development of large-scale integrated-circuit (LSI) technology, the implementation cost of associative processors will be greatly reduced and it is anticipated that associative processors will be used more extensively for enhancing the performance of many special-purpose and general-purpose computer systems. Although there have been several papers providing either tutorials or literature surveys on associative processors [1][2][3][4][5], a number of new developments have not been described in any of the previous survey papers. In this paper, we will present a survey of the architecture of various associative processors, with emphasis on their characteristics, categorization, and implementation, and especially recent developments.…”

Section: Introductionmentioning

confidence: 99%

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Associative Processor Architecture—a Survey

Yau

Fung

1977

ACM Comput. Surv.

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A survey of the architecture of various associative processors is presented with emphasis on their characteristics, categorization, and implementation, and especially on recent developments. Based on their architecture, associative processors are classified into four categories, namely fully parallel, bit-serial, word-serial and block-oriented. The fully parallel associative processors are divided into two classes, word-orgamzed and distributed logic associative processors. Keywords and Phrases:Associative processors, computer architecture, categomzation, implementation, hardware, large-scale integration, fully parallel, bit-serial, word-serial, block-ormnted, distributed logic CR Categories: 3. 80, 6.22, 6.30, 6.31, 6.32, 6.33, 6.34 INTRODUCTIONAn associative processor can generally be described as a processor which has the following two properties: 1) Stored data items can be retrieved using their content or part of their content (instead of their addresses); and 2) data transformation operations, both arithmetic and logical, can be performed over many sets of arguments with a single instruction. Because of these parallel processing characteristics, associative processors have a much faster data processing rate than conventional sequential computers, and hence are more effective in handling many types of information processing problems such as information storage and retrieval of rapidly changing databases, fast search of a large database, arithmetic and logical operations on large sets of data, control and executive functions in large-scale computer systems, radar signal tracking and processing, and weather prediction computations. However, because of their relatively high implementation cost, associative processors are usually used in conjunction with standard sequential computer systems so that many required highspeed parallel processing tasks which cannot be effectively executed by sequential processors are performed by associative processors. Because of the rapid development of large-scale integrated-circuit (LSI) technology, the implementation cost of associative processors will be greatly reduced and it is anticipated that associative processors will be used more extensively for enhancing the performance of many special-purpose and general-purpose computer systems. Although there have been several papers providing either tutorials or literature surveys on associative processors [1-5], a number of new developments have not been described in any of the previous survey papers. In this paper, we will present a survey of the architecture of various associative processors, with emphasis on their characteristics, categorization, and implementation, and especially recent developments.

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Section: Associative Memoriesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Associative Processor Architecture—a Survey

Yau

Fung

1977

ACM Comput. Surv.

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“…A decade later, cryogenic elements provided the first viable cell technology for large-scale implementation of associative memories [3]. Further developments in this area are amply documented in various books, article collections, and survey papers [4][5][6][7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

“…Architecturally, associative memories come in four basic varieties: fully parallel, bit-serial, word-serial and block-oriented [10]. Bit-serial systems have been dominant in practical implementations in view of their costeffectiveness [5,13,14].…”

Section: Introductionmentioning

confidence: 99%

Extreme-Value Search and General Selection Algorithms for Fully Parallel Associative Memories

Parhami

1996

The Computer Journal

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Several useful associative memory algorithms deal with identifying extreme values (maximum or minimum) in a specified field of a selected subset of words. Previously proposed algorithms for such extreme-value searches are bit-sequential in nature, even when implemented on fully parallel associative memories. We show how the multiple-bit search capability of a fully parallel associative memory can be used to advantage in reducing the expected search time for finding extreme values. The idea is to search for the all-ones pattern within subfields of the specified search field in lieu of, or prior to, examining bit slices one at a time. Optimal subfield length is determined for both fixed-size and variable-size bit groupings and the corresponding reduction in search time is quantified. The results are extended to rank-based selection where the jth largest or smallest value in a given field of a selected subset of words is to be identified. We conclude that significant reduction in the number of search cycles is possible in most practical extreme-value search and selection problems.

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“…Owing to their addressing mechanisms, these memories are superior to random access memories (RAMS) in several applications, such as searching, data retrieval, memory mapping, and the like. An extensive survey of such applications is given by Parhami [21]. However, the associative memories have always been more costly than conventional memories (RAMS) because they require more circuitry per memory cell.…”

Section: Introductionmentioning

confidence: 99%

Associative table lookup processing for multioperand residue arithmetic

Papachristou

1987

J. ACM

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This paper investigates the complexity of multioperand residue addition and multiplication implemented by associative table lookup processing. The complexity measure used is the size of the associative memory, that is, the number of matching words in memory. This measure largely depends on the residue recurrencies, or multiplicities, in the addition and multiplication tables modulo M. The major effort in this work is to evaluate the recurrencies in simultaneous multioperand residue addition and multiplication. The evaluation is simple in case of addition modM, and also in multiplication mod&f if M is prime. To treat the more difficult case of M nonprime, a recursive procedure was developed for computing the 2-operand multiplication recurrencies modM. The basis of this technique is the precedence relationships associated with a tree representation of the factors of M. It is then shown that the general D-operand multiplication modM, D > 2 and M nonprime, can be reduced to the 2-operand case by isomorphic transformation. Computation results of 2-operand residue arithmetic operations are provided. Applications to RNS arithmetic implementation are discussed.

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Associative memories and processors: An overview and selected bibliography

Cited by 66 publications

References 103 publications

Associative Processor Architecture—a Survey

Associative Processor Architecture—a Survey

Extreme-Value Search and General Selection Algorithms for Fully Parallel Associative Memories

Associative table lookup processing for multioperand residue arithmetic

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