Associative ternary cache for IP routing

Abstract

Abstract. In this paper we present a study of a prefix routing cache for Internet IP routing. An output port assignment requires one cache memory access when the assignment is found in cache. The cache array is divided into sets that are of variable size; all entries within a set have the same prefix size. The cache is based on a ternary content addressable memory (TCAM) that matches 1, 0 and don't care (X) values. Our study shows that an associative ternary cache provides an output port at the speed of one memory access with a very high hit rate. For an 8K-entry cache the hit rate ranges from 97.62% to 99.67% on traces of 0.2 to 3.5 million addresses. A port error occurs when the port selected by the cache differs from the port that would have been selected from the routing table. In this paper we introduce a novel sampling technique that reduces the worst port error rate by an order of magnitude (from 0.52% to 0.05%).

A Novel Cache Architecture and Placement Framework for Packet Forwarding Engines

“…A number of caching-based solutions have been proposed to speedup packet forwarding algorithms [2], [5], [6], [18], [28]. Before we discuss these schemes in detail, a few common organizational features of these caches are discussed.…”

“…Attempts at caching for IP-forwarding can be broadly classified into two categories: caching address ranges or prefixes [5], [6] and caching data structures used for IP-lookup [2]. Among prefix caching proposals, an associative ternary cache [28] is organized such that cache lines are ordered based on prefix lengths. The appropriate bits of the incoming address are compared with all cached prefixes and longest prefix match is then chosen through a priority encoder.…”