2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems 2013
DOI: 10.1109/vlsid.2013.204
|View full text |Cite
|
Sign up to set email alerts
|

At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems

Abstract: Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the reference voltage level (Vref) in the receiver. The traditional method to choose Vref is to sweep the reference voltage level while performing a link Bit Error Rate (BER) test. This existing method has serious disadvantages like additional circuitry, system overhead and … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 8 publications
(6 reference statements)
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?