Automatic generation of polynomial-based hardware architectures for function evaluation

Dinechin, Florent de; Joldeş, Mioara; Pasca, Bogdan

doi:10.1109/asap.2010.5540952

Cited by 44 publications

(55 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Note that in order to achieve maximum DSP block frequency, it is necessary to add an additional register stage any time a DSP block output is passed to LUTs (for implemented small adders for example). This has not been taken into account in [29] and [13], but is done by default in this work.…”

Section: Fpga Computationmentioning

confidence: 99%

See 1 more Smart Citation

Square-rich fixed point polynomial evaluation on FPGAs

Xu¹,

Fahmy

McLoughlin

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

Polynomial evaluation is important across a wide range of application domains, so significant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial computation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an efficient polynomial evaluation algorithm, which reforms the evaluation process to include an increased number of squaring steps. By using a squarer design that is more efficient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5 th degree polynomials.

show abstract

Section: Fpga Computationmentioning

confidence: 99%

“…Horner's rule is a basic and widely used method for computing polynomials, and is used in numerous complex applications [13,14,15,16]. It works by transforming the polynomial into a series of multiply-add operations.…”

Section: Horner's Rulementioning

confidence: 99%

Square-rich fixed point polynomial evaluation on FPGAs

Xu¹,

Fahmy

McLoughlin

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

show abstract

“…The last option we have explored is a wrapper of the generic polynomial evaluator presented in [4] in the range reduction of Section 2.…”

Section: Architecture Using a Generic Polynomial Evaluatormentioning

confidence: 99%

“…We chose Taylor series over generic polynomial approximation as in [4], for two reasons. The first is that the sine series is odd and the cosine series is even, so their evaluation requires half as many multiplications for a given degree.…”

Section: Algorithmmentioning

confidence: 99%

Fixed-point trigonometric functions on FPGAs

Dinechin

Istoan

Sergent

2013

SIGARCH Comput. Archit. News

Self Cite

View full text Add to dashboard Cite

Three approaches for computing sines and cosines on FPGAs are studied in this paper, with a focus of highthroughput pipelined architecture, and state-of-the-art implementation techniques. The first approach is the classical CORDIC iteration, for which we suggest a reduced iteration technique and fine optimizations in datapath width and latency. The second is an ad-hoc architecture specifically designed around trigonometric identities. The third uses a generic table-and DSP-based polynomial approximator. These three architectures are implemented and compared in the FloPoCo framework.

show abstract

“…For larger values of w F , a generic polynomial evaluator [21] is used as a black box. It inputs a function of…”

Section: Polynomial Approximation For Large Precisionsmentioning

confidence: 99%

A parameterized floating-point exponential function for FPGAs

Detrey

Dinechin

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

View full text Add to dashboard Cite

Abstract-This article presents a generator of floating-point exponential operators targeting recent FPGAs with embedded memories and DSP blocks. A single-precision operator consumes just one DSP block, 18Kbits of dual-port memory, and 392 slices on Virtex-4. For larger precisions, a generic approach based on polynomial approximation is used and proves more resourceefficient than the literature. For instance a double-precision operator consumes 5 BlockRAM and 12 DSP48 blocks on Virtex-5, or 10 M9k and 22 18x18 multipliers on Stratix III. This approach is flexible and is demonstrated to scale up to quadrupleprecision, while enabling frequencies close to the FPGA's nominal frequency. All the proposed architectures are last-bit accurate for all the floating-point range. They are available in the open-source FloPoCo framework.

show abstract

Automatic generation of polynomial-based hardware architectures for function evaluation

Abstract: Abstract

Cited by 44 publications

References 15 publications

Square-rich fixed point polynomial evaluation on FPGAs

Square-rich fixed point polynomial evaluation on FPGAs

Fixed-point trigonometric functions on FPGAs

A parameterized floating-point exponential function for FPGAs

Contact Info

Product

Resources

About